config [31mCONFIG_BF51x[0m
def_bool y
depends on ([31mCONFIG_BF512[0m || [31mCONFIG_BF514[0m || [31mCONFIG_BF516[0m || [31mCONFIG_BF518[0m)
if ([31mCONFIG_BF51x[0m)
source "arch/blackfin/mach-bf518/boards/Kconfig"
menu "BF518 Specific Configuration"
comment "Alternative Multiplexing Scheme"
choice
prompt "PWM Channel Pins"
default [31mCONFIG_BF518_PWM_ALL_PORTF[0m
help
Select pins used for the [31mCONFIG_PWM[0m channels:
PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH PWM_CL
See the Hardware Reference Manual for more details.
config [31mCONFIG_BF518_PWM_ALL_PORTF[0m
bool "PF1 - PF6"
help
PF{1,2,3,4,5,6} <-> PWM_{AH,AL,BH,BL,CH,CL}
config [31mCONFIG_BF518_PWM_PORTF_PORTG[0m
bool "PF11 - PF14 / PG1 - PG2"
help
PF{11,12,13,14} <-> PWM_{AH,AL,BH,BL}
PG{1,2} <-> PWM_{CH,CL}
endchoice
choice
prompt "PWM Sync Pin"
default [31mCONFIG_BF518_PWM_SYNC_PF7[0m
help
Select the pin used for PWM_SYNC.
See the Hardware Reference Manual for more details.
config [31mCONFIG_BF518_PWM_SYNC_PF7[0m
bool "PF7"
config [31mCONFIG_BF518_PWM_SYNC_PF15[0m
bool "PF15"
endchoice
choice
prompt "PWM Trip B Pin"
default [31mCONFIG_BF518_PWM_TRIPB_PG10[0m
help
Select the pin used for PWM_TRIPB.
See the Hardware Reference Manual for more details.
config [31mCONFIG_BF518_PWM_TRIPB_PG10[0m
bool "PG10"
config [31mCONFIG_BF518_PWM_TRIPB_PG14[0m
bool "PG14"
endchoice
choice
prompt "PPI / Timer Pins"
default [31mCONFIG_BF518_PPI_TMR_PG5[0m
help
Select pins used for PPI/Timer:
PPICLK PPIFS1 PPIFS2
TMRCLK TMR0 TMR1
See the Hardware Reference Manual for more details.
config [31mCONFIG_BF518_PPI_TMR_PG5[0m
bool "PG5 - PG7"
help
PG{5,6,7} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
config [31mCONFIG_BF518_PPI_TMR_PG12[0m
bool "PG12 - PG14"
help
PG{12,13,14} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
endchoice
comment "Hysteresis/Schmitt Trigger Control"
config [31mCONFIG_BFIN_HYSTERESIS_CONTROL[0m
bool "Enable Hysteresis Control"
help
The ADSP-[31mCONFIG_BF51x[0m allows to control input hysteresis for Port F,
Port [31mCONFIG_G[0m and Port H and other processor signal inputs.
The Schmitt trigger enables can be set only for pin groups.
Saying Y will overwrite the default reset or boot loader
initialization.
menu "PORT F"
depends on [31mCONFIG_BFIN_HYSTERESIS_CONTROL[0m
config [31mCONFIG_GPIO_HYST_PORTF_0_7[0m
bool "Enable Hysteresis on PORTF {0...7}"
config [31mCONFIG_GPIO_HYST_PORTF_8_9[0m
bool "Enable Hysteresis on PORTF {8, 9}"
config [31mCONFIG_GPIO_HYST_PORTF_10[0m
bool "Enable Hysteresis on PORTF 10"
config [31mCONFIG_GPIO_HYST_PORTF_11[0m
bool "Enable Hysteresis on PORTF 11"
config [31mCONFIG_GPIO_HYST_PORTF_12_13[0m
bool "Enable Hysteresis on PORTF {12, 13}"
config [31mCONFIG_GPIO_HYST_PORTF_14_15[0m
bool "Enable Hysteresis on PORTF {14, 15}"
endmenu
menu "PORT G"
depends on [31mCONFIG_BFIN_HYSTERESIS_CONTROL[0m
config [31mCONFIG_GPIO_HYST_PORTG_0[0m
bool "Enable Hysteresis on PORTG 0"
config [31mCONFIG_GPIO_HYST_PORTG_1_4[0m
bool "Enable Hysteresis on PORTG {1...4}"
config [31mCONFIG_GPIO_HYST_PORTG_5_6[0m
bool "Enable Hysteresis on PORTG {5, 6}"
config [31mCONFIG_GPIO_HYST_PORTG_7_8[0m
bool "Enable Hysteresis on PORTG {7, 8}"
config [31mCONFIG_GPIO_HYST_PORTG_9[0m
bool "Enable Hysteresis on PORTG 9"
config [31mCONFIG_GPIO_HYST_PORTG_10[0m
bool "Enable Hysteresis on PORTG 10"
config [31mCONFIG_GPIO_HYST_PORTG_11_13[0m
bool "Enable Hysteresis on PORTG {11...13}"
config [31mCONFIG_GPIO_HYST_PORTG_14_15[0m
bool "Enable Hysteresis on PORTG {14, 15}"
endmenu
menu "PORT H"
depends on [31mCONFIG_BFIN_HYSTERESIS_CONTROL[0m
config [31mCONFIG_GPIO_HYST_PORTH_0_7[0m
bool "Enable Hysteresis on PORTH {0...7}"
endmenu
menu "None-GPIO"
depends on [31mCONFIG_BFIN_HYSTERESIS_CONTROL[0m
config [31mCONFIG_NONEGPIO_HYST_NMI_RST_BMODE[0m
bool "Enable Hysteresis on {NMI, RESET, BMODE}"
config [31mCONFIG_NONEGPIO_HYST_JTAG[0m
bool "Enable Hysteresis on JTAG"
endmenu
comment "Interrupt Priority Assignment"
menu "Priority"
config [31mCONFIG_IRQ_PLL_WAKEUP[0m
int "IRQ_PLL_WAKEUP"
default 7
config [31mCONFIG_IRQ_DMA0_ERROR[0m
int "IRQ_DMA0_ERROR"
default 7
config [31mCONFIG_IRQ_DMAR0_BLK[0m
int "IRQ_DMAR0_BLK"
default 7
config [31mCONFIG_IRQ_DMAR1_BLK[0m
int "IRQ_DMAR1_BLK"
default 7
config [31mCONFIG_IRQ_DMAR0_OVR[0m
int "IRQ_DMAR0_OVR"
default 7
config [31mCONFIG_IRQ_DMAR1_OVR[0m
int "IRQ_DMAR1_OVR"
default 7
config [31mCONFIG_IRQ_PPI_ERROR[0m
int "IRQ_PPI_ERROR"
default 7
config [31mCONFIG_IRQ_MAC_ERROR[0m
int "IRQ_MAC_ERROR"
default 7
config [31mCONFIG_IRQ_SPORT0_ERROR[0m
int "IRQ_SPORT0_ERROR"
default 7
config [31mCONFIG_IRQ_SPORT1_ERROR[0m
int "IRQ_SPORT1_ERROR"
default 7
config [31mCONFIG_IRQ_PTP_ERROR[0m
int "IRQ_PTP_ERROR"
default 7
config [31mCONFIG_IRQ_UART0_ERROR[0m
int "IRQ_UART0_ERROR"
default 7
config [31mCONFIG_IRQ_UART1_ERROR[0m
int "IRQ_UART1_ERROR"
default 7
config [31mCONFIG_IRQ_RTC[0m
int "IRQ_RTC"
default 8
config [31mCONFIG_IRQ_PPI[0m
int "IRQ_PPI"
default 8
config [31mCONFIG_IRQ_SPORT0_RX[0m
int "IRQ_SPORT0_RX"
default 9
config [31mCONFIG_IRQ_SPORT0_TX[0m
int "IRQ_SPORT0_TX"
default 9
config [31mCONFIG_IRQ_SPORT1_RX[0m
int "IRQ_SPORT1_RX"
default 9
config [31mCONFIG_IRQ_SPORT1_TX[0m
int "IRQ_SPORT1_TX"
default 9
config [31mCONFIG_IRQ_TWI[0m
int "IRQ_TWI"
default 10
config [31mCONFIG_IRQ_SPI0[0m
int "IRQ_SPI"
default 10
config [31mCONFIG_IRQ_UART0_RX[0m
int "IRQ_UART0_RX"
default 10
config [31mCONFIG_IRQ_UART0_TX[0m
int "IRQ_UART0_TX"
default 10
config [31mCONFIG_IRQ_UART1_RX[0m
int "IRQ_UART1_RX"
default 10
config [31mCONFIG_IRQ_UART1_TX[0m
int "IRQ_UART1_TX"
default 10
config [31mCONFIG_IRQ_OPTSEC[0m
int "IRQ_OPTSEC"
default 11
config [31mCONFIG_IRQ_CNT[0m
int "IRQ_CNT"
default 11
config [31mCONFIG_IRQ_MAC_RX[0m
int "IRQ_MAC_RX"
default 11
config [31mCONFIG_IRQ_PORTH_INTA[0m
int "IRQ_PORTH_INTA"
default 11
config [31mCONFIG_IRQ_MAC_TX[0m
int "IRQ_MAC_TX/NFC"
default 11
config [31mCONFIG_IRQ_PORTH_INTB[0m
int "IRQ_PORTH_INTB"
default 11
config [31mCONFIG_IRQ_TIMER0[0m
int "IRQ_TIMER0"
default 7 if [31mCONFIG_TICKSOURCE_GPTMR0[0m
default 8
config [31mCONFIG_IRQ_TIMER1[0m
int "IRQ_TIMER1"
default 12
config [31mCONFIG_IRQ_TIMER2[0m
int "IRQ_TIMER2"
default 12
config [31mCONFIG_IRQ_TIMER3[0m
int "IRQ_TIMER3"
default 12
config [31mCONFIG_IRQ_TIMER4[0m
int "IRQ_TIMER4"
default 12
config [31mCONFIG_IRQ_TIMER5[0m
int "IRQ_TIMER5"
default 12
config [31mCONFIG_IRQ_TIMER6[0m
int "IRQ_TIMER6"
default 12
config [31mCONFIG_IRQ_TIMER7[0m
int "IRQ_TIMER7"
default 12
config [31mCONFIG_IRQ_PORTG_INTA[0m
int "IRQ_PORTG_INTA"
default 12
config [31mCONFIG_IRQ_PORTG_INTB[0m
int "IRQ_PORTG_INTB"
default 12
config [31mCONFIG_IRQ_MEM_DMA0[0m
int "IRQ_MEM_DMA0"
default 13
config [31mCONFIG_IRQ_MEM_DMA1[0m
int "IRQ_MEM_DMA1"
default 13
config [31mCONFIG_IRQ_WATCH[0m
int "IRQ_WATCH"
default 13
config [31mCONFIG_IRQ_PORTF_INTA[0m
int "IRQ_PORTF_INTA"
default 13
config [31mCONFIG_IRQ_PORTF_INTB[0m
int "IRQ_PORTF_INTB"
default 13
config [31mCONFIG_IRQ_SPI0_ERROR[0m
int "IRQ_SPI0_ERROR"
default 7
config [31mCONFIG_IRQ_SPI1_ERROR[0m
int "IRQ_SPI1_ERROR"
default 7
config [31mCONFIG_IRQ_RSI_INT0[0m
int "IRQ_RSI_INT0"
default 7
config [31mCONFIG_IRQ_RSI_INT1[0m
int "IRQ_RSI_INT1"
default 7
config [31mCONFIG_IRQ_PWM_TRIP[0m
int "IRQ_PWM_TRIP"
default 10
config [31mCONFIG_IRQ_PWM_SYNC[0m
int "IRQ_PWM_SYNC"
default 10
config [31mCONFIG_IRQ_PTP_STAT[0m
int "IRQ_PTP_STAT"
default 10
help
Enter the priority numbers between 7-13 ONLY. Others are Reserved.
This applies to all the above. It is not recommended to assign the
highest priority number 7 to UART or any other device.
endmenu
endmenu
endif