config [31mCONFIG_SIBYTE_SB1250[0m
bool
select [31mCONFIG_CEVT_SB1250[0m
select [31mCONFIG_CSRC_SB1250[0m
select [31mCONFIG_HW_HAS_PCI[0m
select [31mCONFIG_IRQ_MIPS_CPU[0m
select [31mCONFIG_SIBYTE_ENABLE_LDT_IF_PCI[0m
select [31mCONFIG_SIBYTE_HAS_ZBUS_PROFILING[0m
select [31mCONFIG_SIBYTE_SB1xxx_SOC[0m
select [31mCONFIG_SYS_SUPPORTS_SMP[0m
config [31mCONFIG_SIBYTE_BCM1120[0m
bool
select [31mCONFIG_CEVT_SB1250[0m
select [31mCONFIG_CSRC_SB1250[0m
select [31mCONFIG_IRQ_MIPS_CPU[0m
select [31mCONFIG_SIBYTE_BCM112X[0m
select [31mCONFIG_SIBYTE_HAS_ZBUS_PROFILING[0m
select [31mCONFIG_SIBYTE_SB1xxx_SOC[0m
config [31mCONFIG_SIBYTE_BCM1125[0m
bool
select [31mCONFIG_CEVT_SB1250[0m
select [31mCONFIG_CSRC_SB1250[0m
select [31mCONFIG_HW_HAS_PCI[0m
select [31mCONFIG_IRQ_MIPS_CPU[0m
select [31mCONFIG_SIBYTE_BCM112X[0m
select [31mCONFIG_SIBYTE_HAS_ZBUS_PROFILING[0m
select [31mCONFIG_SIBYTE_SB1xxx_SOC[0m
config [31mCONFIG_SIBYTE_BCM1125H[0m
bool
select [31mCONFIG_CEVT_SB1250[0m
select [31mCONFIG_CSRC_SB1250[0m
select [31mCONFIG_HW_HAS_PCI[0m
select [31mCONFIG_IRQ_MIPS_CPU[0m
select [31mCONFIG_SIBYTE_BCM112X[0m
select [31mCONFIG_SIBYTE_ENABLE_LDT_IF_PCI[0m
select [31mCONFIG_SIBYTE_HAS_ZBUS_PROFILING[0m
select [31mCONFIG_SIBYTE_SB1xxx_SOC[0m
config [31mCONFIG_SIBYTE_BCM112X[0m
bool
select [31mCONFIG_CEVT_SB1250[0m
select [31mCONFIG_CSRC_SB1250[0m
select [31mCONFIG_IRQ_MIPS_CPU[0m
select [31mCONFIG_SIBYTE_SB1xxx_SOC[0m
select [31mCONFIG_SIBYTE_HAS_ZBUS_PROFILING[0m
config [31mCONFIG_SIBYTE_BCM1x80[0m
bool
select [31mCONFIG_CEVT_BCM1480[0m
select [31mCONFIG_CSRC_BCM1480[0m
select [31mCONFIG_HW_HAS_PCI[0m
select [31mCONFIG_IRQ_MIPS_CPU[0m
select [31mCONFIG_SIBYTE_HAS_ZBUS_PROFILING[0m
select [31mCONFIG_SIBYTE_SB1xxx_SOC[0m
select [31mCONFIG_SYS_SUPPORTS_SMP[0m
config [31mCONFIG_SIBYTE_BCM1x55[0m
bool
select [31mCONFIG_CEVT_BCM1480[0m
select [31mCONFIG_CSRC_BCM1480[0m
select [31mCONFIG_HW_HAS_PCI[0m
select [31mCONFIG_IRQ_MIPS_CPU[0m
select [31mCONFIG_SIBYTE_SB1xxx_SOC[0m
select [31mCONFIG_SIBYTE_HAS_ZBUS_PROFILING[0m
select [31mCONFIG_SYS_SUPPORTS_SMP[0m
config [31mCONFIG_SIBYTE_SB1xxx_SOC[0m
bool
select [31mCONFIG_DMA_COHERENT[0m
select [31mCONFIG_IRQ_MIPS_CPU[0m
select [31mCONFIG_SWAP_IO_SPACE[0m
select [31mCONFIG_SYS_SUPPORTS_32BIT_KERNEL[0m
select [31mCONFIG_SYS_SUPPORTS_64BIT_KERNEL[0m
select [31mCONFIG_FW_CFE[0m
select [31mCONFIG_SYS_HAS_EARLY_PRINTK[0m
choice
prompt "SiByte SOC Stepping"
depends on [31mCONFIG_SIBYTE_SB1xxx_SOC[0m
config [31mCONFIG_CPU_SB1_PASS_2_1250[0m
bool "1250 An"
depends on [31mCONFIG_SIBYTE_SB1250[0m
select [31mCONFIG_CPU_SB1_PASS_2[0m
help
Also called BCM1250 Pass 2
config [31mCONFIG_CPU_SB1_PASS_2_2[0m
bool "1250 Bn"
depends on [31mCONFIG_SIBYTE_SB1250[0m
select [31mCONFIG_CPU_HAS_PREFETCH[0m
help
Also called BCM1250 Pass 2.2
config [31mCONFIG_CPU_SB1_PASS_4[0m
bool "1250 Cn"
depends on [31mCONFIG_SIBYTE_SB1250[0m
select [31mCONFIG_CPU_HAS_PREFETCH[0m
help
Also called BCM1250 Pass 3
config [31mCONFIG_CPU_SB1_PASS_2_112x[0m
bool "112x Hybrid"
depends on [31mCONFIG_SIBYTE_BCM112X[0m
select [31mCONFIG_CPU_SB1_PASS_2[0m
config [31mCONFIG_CPU_SB1_PASS_3[0m
bool "112x An"
depends on [31mCONFIG_SIBYTE_BCM112X[0m
select [31mCONFIG_CPU_HAS_PREFETCH[0m
endchoice
config [31mCONFIG_CPU_SB1_PASS_2[0m
bool
config [31mCONFIG_SIBYTE_HAS_LDT[0m
bool
config [31mCONFIG_SIBYTE_ENABLE_LDT_IF_PCI[0m
bool
select [31mCONFIG_SIBYTE_HAS_LDT[0m if [31mCONFIG_PCI[0m
config [31mCONFIG_SB1_CEX_ALWAYS_FATAL[0m
bool "All cache exceptions considered fatal (no recovery attempted)"
depends on [31mCONFIG_SIBYTE_SB1xxx_SOC[0m
config [31mCONFIG_SB1_CERR_STALL[0m
bool "Stall (rather than panic) on fatal cache error"
depends on [31mCONFIG_SIBYTE_SB1xxx_SOC[0m
config [31mCONFIG_SIBYTE_CFE_CONSOLE[0m
bool "Use firmware console"
depends on [31mCONFIG_SIBYTE_SB1xxx_SOC[0m
help
Use the CFE API's console write routines during boot. Other console
options ([31mCONFIG_VT[0m console, sb1250 duart console, etc.) should not be
configured.
config [31mCONFIG_SIBYTE_BUS_WATCHER[0m
bool "Support for Bus Watcher statistics"
depends on [31mCONFIG_SIBYTE_SB1xxx_SOC[0m && \
([31mCONFIG_SIBYTE_BCM112X[0m || [31mCONFIG_SIBYTE_SB1250[0m || \
[31mCONFIG_SIBYTE_BCM1x55[0m || [31mCONFIG_SIBYTE_BCM1x80[0m)
help
Handle and keep statistics on the bus error interrupts (COR_ECC,
BAD_ECC, IO_BUS).
config [31mCONFIG_SIBYTE_BW_TRACE[0m
bool "Capture bus trace before bus error"
depends on [31mCONFIG_SIBYTE_BUS_WATCHER[0m
help
Run a continuous bus trace, dumping the raw data as soon as
a ZBbus error is detected. Cannot work if ZBbus profiling
is turned on, and also will interfere with JTAG-based trace
buffer activity. Raw buffer data is dumped to console, and
must be processed off-line.
config [31mCONFIG_SIBYTE_TBPROF[0m
tristate "Support for ZBbus profiling"
depends on [31mCONFIG_SIBYTE_HAS_ZBUS_PROFILING[0m
config [31mCONFIG_SIBYTE_HAS_ZBUS_PROFILING[0m
bool