Training courses

Kernel and Embedded Linux

Bootlin training courses

Embedded Linux, kernel,
Yocto Project, Buildroot, real-time,
graphics, boot time, debugging...

Bootlin logo

Elixir Cross Referencer

  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
#ifndef __gio_defs_asm_h
#define __gio_defs_asm_h

/*
 * This file is autogenerated from
 *   file:           gio.r
 * 
 *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */

#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif

#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif

#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif

#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif

#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
			 STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
                          ((inst) + offs + (index) * stride)
#endif

/* Register r_pa_din, scope gio, type r */
#define reg_gio_r_pa_din___data___lsb 0
#define reg_gio_r_pa_din___data___width 32
#define reg_gio_r_pa_din_offset 0

/* Register rw_pa_dout, scope gio, type rw */
#define reg_gio_rw_pa_dout___data___lsb 0
#define reg_gio_rw_pa_dout___data___width 32
#define reg_gio_rw_pa_dout_offset 4

/* Register rw_pa_oe, scope gio, type rw */
#define reg_gio_rw_pa_oe___oe___lsb 0
#define reg_gio_rw_pa_oe___oe___width 32
#define reg_gio_rw_pa_oe_offset 8

/* Register rw_pa_byte0_dout, scope gio, type rw */
#define reg_gio_rw_pa_byte0_dout___data___lsb 0
#define reg_gio_rw_pa_byte0_dout___data___width 8
#define reg_gio_rw_pa_byte0_dout_offset 12

/* Register rw_pa_byte0_oe, scope gio, type rw */
#define reg_gio_rw_pa_byte0_oe___oe___lsb 0
#define reg_gio_rw_pa_byte0_oe___oe___width 8
#define reg_gio_rw_pa_byte0_oe_offset 16

/* Register rw_pa_byte1_dout, scope gio, type rw */
#define reg_gio_rw_pa_byte1_dout___data___lsb 0
#define reg_gio_rw_pa_byte1_dout___data___width 8
#define reg_gio_rw_pa_byte1_dout_offset 20

/* Register rw_pa_byte1_oe, scope gio, type rw */
#define reg_gio_rw_pa_byte1_oe___oe___lsb 0
#define reg_gio_rw_pa_byte1_oe___oe___width 8
#define reg_gio_rw_pa_byte1_oe_offset 24

/* Register rw_pa_byte2_dout, scope gio, type rw */
#define reg_gio_rw_pa_byte2_dout___data___lsb 0
#define reg_gio_rw_pa_byte2_dout___data___width 8
#define reg_gio_rw_pa_byte2_dout_offset 28

/* Register rw_pa_byte2_oe, scope gio, type rw */
#define reg_gio_rw_pa_byte2_oe___oe___lsb 0
#define reg_gio_rw_pa_byte2_oe___oe___width 8
#define reg_gio_rw_pa_byte2_oe_offset 32

/* Register rw_pa_byte3_dout, scope gio, type rw */
#define reg_gio_rw_pa_byte3_dout___data___lsb 0
#define reg_gio_rw_pa_byte3_dout___data___width 8
#define reg_gio_rw_pa_byte3_dout_offset 36

/* Register rw_pa_byte3_oe, scope gio, type rw */
#define reg_gio_rw_pa_byte3_oe___oe___lsb 0
#define reg_gio_rw_pa_byte3_oe___oe___width 8
#define reg_gio_rw_pa_byte3_oe_offset 40

/* Register r_pb_din, scope gio, type r */
#define reg_gio_r_pb_din___data___lsb 0
#define reg_gio_r_pb_din___data___width 32
#define reg_gio_r_pb_din_offset 44

/* Register rw_pb_dout, scope gio, type rw */
#define reg_gio_rw_pb_dout___data___lsb 0
#define reg_gio_rw_pb_dout___data___width 32
#define reg_gio_rw_pb_dout_offset 48

/* Register rw_pb_oe, scope gio, type rw */
#define reg_gio_rw_pb_oe___oe___lsb 0
#define reg_gio_rw_pb_oe___oe___width 32
#define reg_gio_rw_pb_oe_offset 52

/* Register rw_pb_byte0_dout, scope gio, type rw */
#define reg_gio_rw_pb_byte0_dout___data___lsb 0
#define reg_gio_rw_pb_byte0_dout___data___width 8
#define reg_gio_rw_pb_byte0_dout_offset 56

/* Register rw_pb_byte0_oe, scope gio, type rw */
#define reg_gio_rw_pb_byte0_oe___oe___lsb 0
#define reg_gio_rw_pb_byte0_oe___oe___width 8
#define reg_gio_rw_pb_byte0_oe_offset 60

/* Register rw_pb_byte1_dout, scope gio, type rw */
#define reg_gio_rw_pb_byte1_dout___data___lsb 0
#define reg_gio_rw_pb_byte1_dout___data___width 8
#define reg_gio_rw_pb_byte1_dout_offset 64

/* Register rw_pb_byte1_oe, scope gio, type rw */
#define reg_gio_rw_pb_byte1_oe___oe___lsb 0
#define reg_gio_rw_pb_byte1_oe___oe___width 8
#define reg_gio_rw_pb_byte1_oe_offset 68

/* Register rw_pb_byte2_dout, scope gio, type rw */
#define reg_gio_rw_pb_byte2_dout___data___lsb 0
#define reg_gio_rw_pb_byte2_dout___data___width 8
#define reg_gio_rw_pb_byte2_dout_offset 72

/* Register rw_pb_byte2_oe, scope gio, type rw */
#define reg_gio_rw_pb_byte2_oe___oe___lsb 0
#define reg_gio_rw_pb_byte2_oe___oe___width 8
#define reg_gio_rw_pb_byte2_oe_offset 76

/* Register rw_pb_byte3_dout, scope gio, type rw */
#define reg_gio_rw_pb_byte3_dout___data___lsb 0
#define reg_gio_rw_pb_byte3_dout___data___width 8
#define reg_gio_rw_pb_byte3_dout_offset 80

/* Register rw_pb_byte3_oe, scope gio, type rw */
#define reg_gio_rw_pb_byte3_oe___oe___lsb 0
#define reg_gio_rw_pb_byte3_oe___oe___width 8
#define reg_gio_rw_pb_byte3_oe_offset 84

/* Register r_pc_din, scope gio, type r */
#define reg_gio_r_pc_din___data___lsb 0
#define reg_gio_r_pc_din___data___width 16
#define reg_gio_r_pc_din_offset 88

/* Register rw_pc_dout, scope gio, type rw */
#define reg_gio_rw_pc_dout___data___lsb 0
#define reg_gio_rw_pc_dout___data___width 16
#define reg_gio_rw_pc_dout_offset 92

/* Register rw_pc_oe, scope gio, type rw */
#define reg_gio_rw_pc_oe___oe___lsb 0
#define reg_gio_rw_pc_oe___oe___width 16
#define reg_gio_rw_pc_oe_offset 96

/* Register rw_pc_byte0_dout, scope gio, type rw */
#define reg_gio_rw_pc_byte0_dout___data___lsb 0
#define reg_gio_rw_pc_byte0_dout___data___width 8
#define reg_gio_rw_pc_byte0_dout_offset 100

/* Register rw_pc_byte0_oe, scope gio, type rw */
#define reg_gio_rw_pc_byte0_oe___oe___lsb 0
#define reg_gio_rw_pc_byte0_oe___oe___width 8
#define reg_gio_rw_pc_byte0_oe_offset 104

/* Register rw_pc_byte1_dout, scope gio, type rw */
#define reg_gio_rw_pc_byte1_dout___data___lsb 0
#define reg_gio_rw_pc_byte1_dout___data___width 8
#define reg_gio_rw_pc_byte1_dout_offset 108

/* Register rw_pc_byte1_oe, scope gio, type rw */
#define reg_gio_rw_pc_byte1_oe___oe___lsb 0
#define reg_gio_rw_pc_byte1_oe___oe___width 8
#define reg_gio_rw_pc_byte1_oe_offset 112

/* Register r_pd_din, scope gio, type r */
#define reg_gio_r_pd_din___data___lsb 0
#define reg_gio_r_pd_din___data___width 32
#define reg_gio_r_pd_din_offset 116

/* Register rw_intr_cfg, scope gio, type rw */
#define reg_gio_rw_intr_cfg___intr0___lsb 0
#define reg_gio_rw_intr_cfg___intr0___width 3
#define reg_gio_rw_intr_cfg___intr1___lsb 3
#define reg_gio_rw_intr_cfg___intr1___width 3
#define reg_gio_rw_intr_cfg___intr2___lsb 6
#define reg_gio_rw_intr_cfg___intr2___width 3
#define reg_gio_rw_intr_cfg___intr3___lsb 9
#define reg_gio_rw_intr_cfg___intr3___width 3
#define reg_gio_rw_intr_cfg___intr4___lsb 12
#define reg_gio_rw_intr_cfg___intr4___width 3
#define reg_gio_rw_intr_cfg___intr5___lsb 15
#define reg_gio_rw_intr_cfg___intr5___width 3
#define reg_gio_rw_intr_cfg___intr6___lsb 18
#define reg_gio_rw_intr_cfg___intr6___width 3
#define reg_gio_rw_intr_cfg___intr7___lsb 21
#define reg_gio_rw_intr_cfg___intr7___width 3
#define reg_gio_rw_intr_cfg_offset 120

/* Register rw_intr_pins, scope gio, type rw */
#define reg_gio_rw_intr_pins___intr0___lsb 0
#define reg_gio_rw_intr_pins___intr0___width 4
#define reg_gio_rw_intr_pins___intr1___lsb 4
#define reg_gio_rw_intr_pins___intr1___width 4
#define reg_gio_rw_intr_pins___intr2___lsb 8
#define reg_gio_rw_intr_pins___intr2___width 4
#define reg_gio_rw_intr_pins___intr3___lsb 12
#define reg_gio_rw_intr_pins___intr3___width 4
#define reg_gio_rw_intr_pins___intr4___lsb 16
#define reg_gio_rw_intr_pins___intr4___width 4
#define reg_gio_rw_intr_pins___intr5___lsb 20
#define reg_gio_rw_intr_pins___intr5___width 4
#define reg_gio_rw_intr_pins___intr6___lsb 24
#define reg_gio_rw_intr_pins___intr6___width 4
#define reg_gio_rw_intr_pins___intr7___lsb 28
#define reg_gio_rw_intr_pins___intr7___width 4
#define reg_gio_rw_intr_pins_offset 124

/* Register rw_intr_mask, scope gio, type rw */
#define reg_gio_rw_intr_mask___intr0___lsb 0
#define reg_gio_rw_intr_mask___intr0___width 1
#define reg_gio_rw_intr_mask___intr0___bit 0
#define reg_gio_rw_intr_mask___intr1___lsb 1
#define reg_gio_rw_intr_mask___intr1___width 1
#define reg_gio_rw_intr_mask___intr1___bit 1
#define reg_gio_rw_intr_mask___intr2___lsb 2
#define reg_gio_rw_intr_mask___intr2___width 1
#define reg_gio_rw_intr_mask___intr2___bit 2
#define reg_gio_rw_intr_mask___intr3___lsb 3
#define reg_gio_rw_intr_mask___intr3___width 1
#define reg_gio_rw_intr_mask___intr3___bit 3
#define reg_gio_rw_intr_mask___intr4___lsb 4
#define reg_gio_rw_intr_mask___intr4___width 1
#define reg_gio_rw_intr_mask___intr4___bit 4
#define reg_gio_rw_intr_mask___intr5___lsb 5
#define reg_gio_rw_intr_mask___intr5___width 1
#define reg_gio_rw_intr_mask___intr5___bit 5
#define reg_gio_rw_intr_mask___intr6___lsb 6
#define reg_gio_rw_intr_mask___intr6___width 1
#define reg_gio_rw_intr_mask___intr6___bit 6
#define reg_gio_rw_intr_mask___intr7___lsb 7
#define reg_gio_rw_intr_mask___intr7___width 1
#define reg_gio_rw_intr_mask___intr7___bit 7
#define reg_gio_rw_intr_mask___i2c0_done___lsb 8
#define reg_gio_rw_intr_mask___i2c0_done___width 1
#define reg_gio_rw_intr_mask___i2c0_done___bit 8
#define reg_gio_rw_intr_mask___i2c1_done___lsb 9
#define reg_gio_rw_intr_mask___i2c1_done___width 1
#define reg_gio_rw_intr_mask___i2c1_done___bit 9
#define reg_gio_rw_intr_mask_offset 128

/* Register rw_ack_intr, scope gio, type rw */
#define reg_gio_rw_ack_intr___intr0___lsb 0
#define reg_gio_rw_ack_intr___intr0___width 1
#define reg_gio_rw_ack_intr___intr0___bit 0
#define reg_gio_rw_ack_intr___intr1___lsb 1
#define reg_gio_rw_ack_intr___intr1___width 1
#define reg_gio_rw_ack_intr___intr1___bit 1
#define reg_gio_rw_ack_intr___intr2___lsb 2
#define reg_gio_rw_ack_intr___intr2___width 1
#define reg_gio_rw_ack_intr___intr2___bit 2
#define reg_gio_rw_ack_intr___intr3___lsb 3
#define reg_gio_rw_ack_intr___intr3___width 1
#define reg_gio_rw_ack_intr___intr3___bit 3
#define reg_gio_rw_ack_intr___intr4___lsb 4
#define reg_gio_rw_ack_intr___intr4___width 1
#define reg_gio_rw_ack_intr___intr4___bit 4
#define reg_gio_rw_ack_intr___intr5___lsb 5
#define reg_gio_rw_ack_intr___intr5___width 1
#define reg_gio_rw_ack_intr___intr5___bit 5
#define reg_gio_rw_ack_intr___intr6___lsb 6
#define reg_gio_rw_ack_intr___intr6___width 1
#define reg_gio_rw_ack_intr___intr6___bit 6
#define reg_gio_rw_ack_intr___intr7___lsb 7
#define reg_gio_rw_ack_intr___intr7___width 1
#define reg_gio_rw_ack_intr___intr7___bit 7
#define reg_gio_rw_ack_intr___i2c0_done___lsb 8
#define reg_gio_rw_ack_intr___i2c0_done___width 1
#define reg_gio_rw_ack_intr___i2c0_done___bit 8
#define reg_gio_rw_ack_intr___i2c1_done___lsb 9
#define reg_gio_rw_ack_intr___i2c1_done___width 1
#define reg_gio_rw_ack_intr___i2c1_done___bit 9
#define reg_gio_rw_ack_intr_offset 132

/* Register r_intr, scope gio, type r */
#define reg_gio_r_intr___intr0___lsb 0
#define reg_gio_r_intr___intr0___width 1
#define reg_gio_r_intr___intr0___bit 0
#define reg_gio_r_intr___intr1___lsb 1
#define reg_gio_r_intr___intr1___width 1
#define reg_gio_r_intr___intr1___bit 1
#define reg_gio_r_intr___intr2___lsb 2
#define reg_gio_r_intr___intr2___width 1
#define reg_gio_r_intr___intr2___bit 2
#define reg_gio_r_intr___intr3___lsb 3
#define reg_gio_r_intr___intr3___width 1
#define reg_gio_r_intr___intr3___bit 3
#define reg_gio_r_intr___intr4___lsb 4
#define reg_gio_r_intr___intr4___width 1
#define reg_gio_r_intr___intr4___bit 4
#define reg_gio_r_intr___intr5___lsb 5
#define reg_gio_r_intr___intr5___width 1
#define reg_gio_r_intr___intr5___bit 5
#define reg_gio_r_intr___intr6___lsb 6
#define reg_gio_r_intr___intr6___width 1
#define reg_gio_r_intr___intr6___bit 6
#define reg_gio_r_intr___intr7___lsb 7
#define reg_gio_r_intr___intr7___width 1
#define reg_gio_r_intr___intr7___bit 7
#define reg_gio_r_intr___i2c0_done___lsb 8
#define reg_gio_r_intr___i2c0_done___width 1
#define reg_gio_r_intr___i2c0_done___bit 8
#define reg_gio_r_intr___i2c1_done___lsb 9
#define reg_gio_r_intr___i2c1_done___width 1
#define reg_gio_r_intr___i2c1_done___bit 9
#define reg_gio_r_intr_offset 136

/* Register r_masked_intr, scope gio, type r */
#define reg_gio_r_masked_intr___intr0___lsb 0
#define reg_gio_r_masked_intr___intr0___width 1
#define reg_gio_r_masked_intr___intr0___bit 0
#define reg_gio_r_masked_intr___intr1___lsb 1
#define reg_gio_r_masked_intr___intr1___width 1
#define reg_gio_r_masked_intr___intr1___bit 1
#define reg_gio_r_masked_intr___intr2___lsb 2
#define reg_gio_r_masked_intr___intr2___width 1
#define reg_gio_r_masked_intr___intr2___bit 2
#define reg_gio_r_masked_intr___intr3___lsb 3
#define reg_gio_r_masked_intr___intr3___width 1
#define reg_gio_r_masked_intr___intr3___bit 3
#define reg_gio_r_masked_intr___intr4___lsb 4
#define reg_gio_r_masked_intr___intr4___width 1
#define reg_gio_r_masked_intr___intr4___bit 4
#define reg_gio_r_masked_intr___intr5___lsb 5
#define reg_gio_r_masked_intr___intr5___width 1
#define reg_gio_r_masked_intr___intr5___bit 5
#define reg_gio_r_masked_intr___intr6___lsb 6
#define reg_gio_r_masked_intr___intr6___width 1
#define reg_gio_r_masked_intr___intr6___bit 6
#define reg_gio_r_masked_intr___intr7___lsb 7
#define reg_gio_r_masked_intr___intr7___width 1
#define reg_gio_r_masked_intr___intr7___bit 7
#define reg_gio_r_masked_intr___i2c0_done___lsb 8
#define reg_gio_r_masked_intr___i2c0_done___width 1
#define reg_gio_r_masked_intr___i2c0_done___bit 8
#define reg_gio_r_masked_intr___i2c1_done___lsb 9
#define reg_gio_r_masked_intr___i2c1_done___width 1
#define reg_gio_r_masked_intr___i2c1_done___bit 9
#define reg_gio_r_masked_intr_offset 140

/* Register rw_i2c0_start, scope gio, type rw */
#define reg_gio_rw_i2c0_start___run___lsb 0
#define reg_gio_rw_i2c0_start___run___width 1
#define reg_gio_rw_i2c0_start___run___bit 0
#define reg_gio_rw_i2c0_start_offset 144

/* Register rw_i2c0_cfg, scope gio, type rw */
#define reg_gio_rw_i2c0_cfg___en___lsb 0
#define reg_gio_rw_i2c0_cfg___en___width 1
#define reg_gio_rw_i2c0_cfg___en___bit 0
#define reg_gio_rw_i2c0_cfg___bit_order___lsb 1
#define reg_gio_rw_i2c0_cfg___bit_order___width 1
#define reg_gio_rw_i2c0_cfg___bit_order___bit 1
#define reg_gio_rw_i2c0_cfg___scl_io___lsb 2
#define reg_gio_rw_i2c0_cfg___scl_io___width 1
#define reg_gio_rw_i2c0_cfg___scl_io___bit 2
#define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3
#define reg_gio_rw_i2c0_cfg___scl_inv___width 1
#define reg_gio_rw_i2c0_cfg___scl_inv___bit 3
#define reg_gio_rw_i2c0_cfg___sda_io___lsb 4
#define reg_gio_rw_i2c0_cfg___sda_io___width 1
#define reg_gio_rw_i2c0_cfg___sda_io___bit 4
#define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5
#define reg_gio_rw_i2c0_cfg___sda_idle___width 1
#define reg_gio_rw_i2c0_cfg___sda_idle___bit 5
#define reg_gio_rw_i2c0_cfg_offset 148

/* Register rw_i2c0_ctrl, scope gio, type rw */
#define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0
#define reg_gio_rw_i2c0_ctrl___trf_bits___width 6
#define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6
#define reg_gio_rw_i2c0_ctrl___switch_dir___width 6
#define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12
#define reg_gio_rw_i2c0_ctrl___extra_start___width 3
#define reg_gio_rw_i2c0_ctrl___early_end___lsb 15
#define reg_gio_rw_i2c0_ctrl___early_end___width 1
#define reg_gio_rw_i2c0_ctrl___early_end___bit 15
#define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16
#define reg_gio_rw_i2c0_ctrl___start_stop___width 1
#define reg_gio_rw_i2c0_ctrl___start_stop___bit 16
#define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17
#define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17
#define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18
#define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18
#define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19
#define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19
#define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20
#define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20
#define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21
#define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21
#define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22
#define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1
#define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22
#define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23
#define reg_gio_rw_i2c0_ctrl___ack_bit___width 1
#define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23
#define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24
#define reg_gio_rw_i2c0_ctrl___start_bit___width 1
#define reg_gio_rw_i2c0_ctrl___start_bit___bit 24
#define reg_gio_rw_i2c0_ctrl___freq___lsb 25
#define reg_gio_rw_i2c0_ctrl___freq___width 2
#define reg_gio_rw_i2c0_ctrl_offset 152

/* Register rw_i2c0_data, scope gio, type rw */
#define reg_gio_rw_i2c0_data___data0___lsb 0
#define reg_gio_rw_i2c0_data___data0___width 8
#define reg_gio_rw_i2c0_data___data1___lsb 8
#define reg_gio_rw_i2c0_data___data1___width 8
#define reg_gio_rw_i2c0_data___data2___lsb 16
#define reg_gio_rw_i2c0_data___data2___width 8
#define reg_gio_rw_i2c0_data___data3___lsb 24
#define reg_gio_rw_i2c0_data___data3___width 8
#define reg_gio_rw_i2c0_data_offset 156

/* Register rw_i2c0_data2, scope gio, type rw */
#define reg_gio_rw_i2c0_data2___data4___lsb 0
#define reg_gio_rw_i2c0_data2___data4___width 8
#define reg_gio_rw_i2c0_data2___data5___lsb 8
#define reg_gio_rw_i2c0_data2___data5___width 8
#define reg_gio_rw_i2c0_data2___start_val___lsb 16
#define reg_gio_rw_i2c0_data2___start_val___width 6
#define reg_gio_rw_i2c0_data2___ack_val___lsb 22
#define reg_gio_rw_i2c0_data2___ack_val___width 6
#define reg_gio_rw_i2c0_data2_offset 160

/* Register rw_i2c1_start, scope gio, type rw */
#define reg_gio_rw_i2c1_start___run___lsb 0
#define reg_gio_rw_i2c1_start___run___width 1
#define reg_gio_rw_i2c1_start___run___bit 0
#define reg_gio_rw_i2c1_start_offset 164

/* Register rw_i2c1_cfg, scope gio, type rw */
#define reg_gio_rw_i2c1_cfg___en___lsb 0
#define reg_gio_rw_i2c1_cfg___en___width 1
#define reg_gio_rw_i2c1_cfg___en___bit 0
#define reg_gio_rw_i2c1_cfg___bit_order___lsb 1
#define reg_gio_rw_i2c1_cfg___bit_order___width 1
#define reg_gio_rw_i2c1_cfg___bit_order___bit 1
#define reg_gio_rw_i2c1_cfg___scl_io___lsb 2
#define reg_gio_rw_i2c1_cfg___scl_io___width 1
#define reg_gio_rw_i2c1_cfg___scl_io___bit 2
#define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3
#define reg_gio_rw_i2c1_cfg___scl_inv___width 1
#define reg_gio_rw_i2c1_cfg___scl_inv___bit 3
#define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4
#define reg_gio_rw_i2c1_cfg___sda0_io___width 1
#define reg_gio_rw_i2c1_cfg___sda0_io___bit 4
#define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5
#define reg_gio_rw_i2c1_cfg___sda0_idle___width 1
#define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5
#define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6
#define reg_gio_rw_i2c1_cfg___sda1_io___width 1
#define reg_gio_rw_i2c1_cfg___sda1_io___bit 6
#define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7
#define reg_gio_rw_i2c1_cfg___sda1_idle___width 1
#define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7
#define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8
#define reg_gio_rw_i2c1_cfg___sda2_io___width 1
#define reg_gio_rw_i2c1_cfg___sda2_io___bit 8
#define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9
#define reg_gio_rw_i2c1_cfg___sda2_idle___width 1
#define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9
#define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10
#define reg_gio_rw_i2c1_cfg___sda3_io___width 1
#define reg_gio_rw_i2c1_cfg___sda3_io___bit 10
#define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11
#define reg_gio_rw_i2c1_cfg___sda3_idle___width 1
#define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11
#define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12
#define reg_gio_rw_i2c1_cfg___sda_sel___width 2
#define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14
#define reg_gio_rw_i2c1_cfg___sen_idle___width 1
#define reg_gio_rw_i2c1_cfg___sen_idle___bit 14
#define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15
#define reg_gio_rw_i2c1_cfg___sen_inv___width 1
#define reg_gio_rw_i2c1_cfg___sen_inv___bit 15
#define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16
#define reg_gio_rw_i2c1_cfg___sen_sel___width 2
#define reg_gio_rw_i2c1_cfg_offset 168

/* Register rw_i2c1_ctrl, scope gio, type rw */
#define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0
#define reg_gio_rw_i2c1_ctrl___trf_bits___width 6
#define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6
#define reg_gio_rw_i2c1_ctrl___switch_dir___width 6
#define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12
#define reg_gio_rw_i2c1_ctrl___extra_start___width 3
#define reg_gio_rw_i2c1_ctrl___early_end___lsb 15
#define reg_gio_rw_i2c1_ctrl___early_end___width 1
#define reg_gio_rw_i2c1_ctrl___early_end___bit 15
#define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16
#define reg_gio_rw_i2c1_ctrl___start_stop___width 1
#define reg_gio_rw_i2c1_ctrl___start_stop___bit 16
#define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17
#define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17
#define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18
#define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18
#define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19
#define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19
#define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20
#define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20
#define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21
#define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21
#define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22
#define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1
#define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22
#define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23
#define reg_gio_rw_i2c1_ctrl___ack_bit___width 1
#define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23
#define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24
#define reg_gio_rw_i2c1_ctrl___start_bit___width 1
#define reg_gio_rw_i2c1_ctrl___start_bit___bit 24
#define reg_gio_rw_i2c1_ctrl___freq___lsb 25
#define reg_gio_rw_i2c1_ctrl___freq___width 2
#define reg_gio_rw_i2c1_ctrl_offset 172

/* Register rw_i2c1_data, scope gio, type rw */
#define reg_gio_rw_i2c1_data___data0___lsb 0
#define reg_gio_rw_i2c1_data___data0___width 8
#define reg_gio_rw_i2c1_data___data1___lsb 8
#define reg_gio_rw_i2c1_data___data1___width 8
#define reg_gio_rw_i2c1_data___data2___lsb 16
#define reg_gio_rw_i2c1_data___data2___width 8
#define reg_gio_rw_i2c1_data___data3___lsb 24
#define reg_gio_rw_i2c1_data___data3___width 8
#define reg_gio_rw_i2c1_data_offset 176

/* Register rw_i2c1_data2, scope gio, type rw */
#define reg_gio_rw_i2c1_data2___data4___lsb 0
#define reg_gio_rw_i2c1_data2___data4___width 8
#define reg_gio_rw_i2c1_data2___data5___lsb 8
#define reg_gio_rw_i2c1_data2___data5___width 8
#define reg_gio_rw_i2c1_data2___start_val___lsb 16
#define reg_gio_rw_i2c1_data2___start_val___width 6
#define reg_gio_rw_i2c1_data2___ack_val___lsb 22
#define reg_gio_rw_i2c1_data2___ack_val___width 6
#define reg_gio_rw_i2c1_data2_offset 180

/* Register r_ppwm_stat, scope gio, type r */
#define reg_gio_r_ppwm_stat___freq___lsb 0
#define reg_gio_r_ppwm_stat___freq___width 2
#define reg_gio_r_ppwm_stat_offset 184

/* Register rw_ppwm_data, scope gio, type rw */
#define reg_gio_rw_ppwm_data___data___lsb 0
#define reg_gio_rw_ppwm_data___data___width 8
#define reg_gio_rw_ppwm_data_offset 188

/* Register rw_pwm0_ctrl, scope gio, type rw */
#define reg_gio_rw_pwm0_ctrl___mode___lsb 0
#define reg_gio_rw_pwm0_ctrl___mode___width 2
#define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2
#define reg_gio_rw_pwm0_ctrl___ccd_override___width 1
#define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2
#define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3
#define reg_gio_rw_pwm0_ctrl___ccd_val___width 1
#define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3
#define reg_gio_rw_pwm0_ctrl_offset 192

/* Register rw_pwm0_var, scope gio, type rw */
#define reg_gio_rw_pwm0_var___lo___lsb 0
#define reg_gio_rw_pwm0_var___lo___width 13
#define reg_gio_rw_pwm0_var___hi___lsb 13
#define reg_gio_rw_pwm0_var___hi___width 13
#define reg_gio_rw_pwm0_var_offset 196

/* Register rw_pwm0_data, scope gio, type rw */
#define reg_gio_rw_pwm0_data___data___lsb 0
#define reg_gio_rw_pwm0_data___data___width 8
#define reg_gio_rw_pwm0_data_offset 200

/* Register rw_pwm1_ctrl, scope gio, type rw */
#define reg_gio_rw_pwm1_ctrl___mode___lsb 0
#define reg_gio_rw_pwm1_ctrl___mode___width 2
#define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2
#define reg_gio_rw_pwm1_ctrl___ccd_override___width 1
#define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2
#define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3
#define reg_gio_rw_pwm1_ctrl___ccd_val___width 1
#define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3
#define reg_gio_rw_pwm1_ctrl_offset 204

/* Register rw_pwm1_var, scope gio, type rw */
#define reg_gio_rw_pwm1_var___lo___lsb 0
#define reg_gio_rw_pwm1_var___lo___width 13
#define reg_gio_rw_pwm1_var___hi___lsb 13
#define reg_gio_rw_pwm1_var___hi___width 13
#define reg_gio_rw_pwm1_var_offset 208

/* Register rw_pwm1_data, scope gio, type rw */
#define reg_gio_rw_pwm1_data___data___lsb 0
#define reg_gio_rw_pwm1_data___data___width 8
#define reg_gio_rw_pwm1_data_offset 212

/* Register rw_pwm2_ctrl, scope gio, type rw */
#define reg_gio_rw_pwm2_ctrl___mode___lsb 0
#define reg_gio_rw_pwm2_ctrl___mode___width 2
#define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2
#define reg_gio_rw_pwm2_ctrl___ccd_override___width 1
#define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2
#define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3
#define reg_gio_rw_pwm2_ctrl___ccd_val___width 1
#define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3
#define reg_gio_rw_pwm2_ctrl_offset 216

/* Register rw_pwm2_var, scope gio, type rw */
#define reg_gio_rw_pwm2_var___lo___lsb 0
#define reg_gio_rw_pwm2_var___lo___width 13
#define reg_gio_rw_pwm2_var___hi___lsb 13
#define reg_gio_rw_pwm2_var___hi___width 13
#define reg_gio_rw_pwm2_var_offset 220

/* Register rw_pwm2_data, scope gio, type rw */
#define reg_gio_rw_pwm2_data___data___lsb 0
#define reg_gio_rw_pwm2_data___data___width 8
#define reg_gio_rw_pwm2_data_offset 224

/* Register rw_pwm_in_cfg, scope gio, type rw */
#define reg_gio_rw_pwm_in_cfg___pin___lsb 0
#define reg_gio_rw_pwm_in_cfg___pin___width 3
#define reg_gio_rw_pwm_in_cfg_offset 228

/* Register r_pwm_in_lo, scope gio, type r */
#define reg_gio_r_pwm_in_lo___data___lsb 0
#define reg_gio_r_pwm_in_lo___data___width 32
#define reg_gio_r_pwm_in_lo_offset 232

/* Register r_pwm_in_hi, scope gio, type r */
#define reg_gio_r_pwm_in_hi___data___lsb 0
#define reg_gio_r_pwm_in_hi___data___width 32
#define reg_gio_r_pwm_in_hi_offset 236

/* Register r_pwm_in_cnt, scope gio, type r */
#define reg_gio_r_pwm_in_cnt___data___lsb 0
#define reg_gio_r_pwm_in_cnt___data___width 32
#define reg_gio_r_pwm_in_cnt_offset 240


/* Constants */
#define regk_gio_anyedge                          0x00000007
#define regk_gio_f100k                            0x00000000
#define regk_gio_f1562                            0x00000000
#define regk_gio_f195                             0x00000003
#define regk_gio_f1m                              0x00000002
#define regk_gio_f390                             0x00000002
#define regk_gio_f400k                            0x00000001
#define regk_gio_f5m                              0x00000003
#define regk_gio_f781                             0x00000001
#define regk_gio_hi                               0x00000001
#define regk_gio_in                               0x00000000
#define regk_gio_intr_pa0                         0x00000000
#define regk_gio_intr_pa1                         0x00000000
#define regk_gio_intr_pa10                        0x00000001
#define regk_gio_intr_pa11                        0x00000001
#define regk_gio_intr_pa12                        0x00000001
#define regk_gio_intr_pa13                        0x00000001
#define regk_gio_intr_pa14                        0x00000001
#define regk_gio_intr_pa15                        0x00000001
#define regk_gio_intr_pa16                        0x00000002
#define regk_gio_intr_pa17                        0x00000002
#define regk_gio_intr_pa18                        0x00000002
#define regk_gio_intr_pa19                        0x00000002
#define regk_gio_intr_pa2                         0x00000000
#define regk_gio_intr_pa20                        0x00000002
#define regk_gio_intr_pa21                        0x00000002
#define regk_gio_intr_pa22                        0x00000002
#define regk_gio_intr_pa23                        0x00000002
#define regk_gio_intr_pa24                        0x00000003
#define regk_gio_intr_pa25                        0x00000003
#define regk_gio_intr_pa26                        0x00000003
#define regk_gio_intr_pa27                        0x00000003
#define regk_gio_intr_pa28                        0x00000003
#define regk_gio_intr_pa29                        0x00000003
#define regk_gio_intr_pa3                         0x00000000
#define regk_gio_intr_pa30                        0x00000003
#define regk_gio_intr_pa31                        0x00000003
#define regk_gio_intr_pa4                         0x00000000
#define regk_gio_intr_pa5                         0x00000000
#define regk_gio_intr_pa6                         0x00000000
#define regk_gio_intr_pa7                         0x00000000
#define regk_gio_intr_pa8                         0x00000001
#define regk_gio_intr_pa9                         0x00000001
#define regk_gio_intr_pb0                         0x00000004
#define regk_gio_intr_pb1                         0x00000004
#define regk_gio_intr_pb10                        0x00000005
#define regk_gio_intr_pb11                        0x00000005
#define regk_gio_intr_pb12                        0x00000005
#define regk_gio_intr_pb13                        0x00000005
#define regk_gio_intr_pb14                        0x00000005
#define regk_gio_intr_pb15                        0x00000005
#define regk_gio_intr_pb16                        0x00000006
#define regk_gio_intr_pb17                        0x00000006
#define regk_gio_intr_pb18                        0x00000006
#define regk_gio_intr_pb19                        0x00000006
#define regk_gio_intr_pb2                         0x00000004
#define regk_gio_intr_pb20                        0x00000006
#define regk_gio_intr_pb21                        0x00000006
#define regk_gio_intr_pb22                        0x00000006
#define regk_gio_intr_pb23                        0x00000006
#define regk_gio_intr_pb24                        0x00000007
#define regk_gio_intr_pb25                        0x00000007
#define regk_gio_intr_pb26                        0x00000007
#define regk_gio_intr_pb27                        0x00000007
#define regk_gio_intr_pb28                        0x00000007
#define regk_gio_intr_pb29                        0x00000007
#define regk_gio_intr_pb3                         0x00000004
#define regk_gio_intr_pb30                        0x00000007
#define regk_gio_intr_pb31                        0x00000007
#define regk_gio_intr_pb4                         0x00000004
#define regk_gio_intr_pb5                         0x00000004
#define regk_gio_intr_pb6                         0x00000004
#define regk_gio_intr_pb7                         0x00000004
#define regk_gio_intr_pb8                         0x00000005
#define regk_gio_intr_pb9                         0x00000005
#define regk_gio_intr_pc0                         0x00000008
#define regk_gio_intr_pc1                         0x00000008
#define regk_gio_intr_pc10                        0x00000009
#define regk_gio_intr_pc11                        0x00000009
#define regk_gio_intr_pc12                        0x00000009
#define regk_gio_intr_pc13                        0x00000009
#define regk_gio_intr_pc14                        0x00000009
#define regk_gio_intr_pc15                        0x00000009
#define regk_gio_intr_pc2                         0x00000008
#define regk_gio_intr_pc3                         0x00000008
#define regk_gio_intr_pc4                         0x00000008
#define regk_gio_intr_pc5                         0x00000008
#define regk_gio_intr_pc6                         0x00000008
#define regk_gio_intr_pc7                         0x00000008
#define regk_gio_intr_pc8                         0x00000009
#define regk_gio_intr_pc9                         0x00000009
#define regk_gio_intr_pd0                         0x0000000c
#define regk_gio_intr_pd1                         0x0000000c
#define regk_gio_intr_pd10                        0x0000000d
#define regk_gio_intr_pd11                        0x0000000d
#define regk_gio_intr_pd12                        0x0000000d
#define regk_gio_intr_pd13                        0x0000000d
#define regk_gio_intr_pd14                        0x0000000d
#define regk_gio_intr_pd15                        0x0000000d
#define regk_gio_intr_pd16                        0x0000000e
#define regk_gio_intr_pd17                        0x0000000e
#define regk_gio_intr_pd18                        0x0000000e
#define regk_gio_intr_pd19                        0x0000000e
#define regk_gio_intr_pd2                         0x0000000c
#define regk_gio_intr_pd20                        0x0000000e
#define regk_gio_intr_pd21                        0x0000000e
#define regk_gio_intr_pd22                        0x0000000e
#define regk_gio_intr_pd23                        0x0000000e
#define regk_gio_intr_pd24                        0x0000000f
#define regk_gio_intr_pd25                        0x0000000f
#define regk_gio_intr_pd26                        0x0000000f
#define regk_gio_intr_pd27                        0x0000000f
#define regk_gio_intr_pd28                        0x0000000f
#define regk_gio_intr_pd29                        0x0000000f
#define regk_gio_intr_pd3                         0x0000000c
#define regk_gio_intr_pd30                        0x0000000f
#define regk_gio_intr_pd31                        0x0000000f
#define regk_gio_intr_pd4                         0x0000000c
#define regk_gio_intr_pd5                         0x0000000c
#define regk_gio_intr_pd6                         0x0000000c
#define regk_gio_intr_pd7                         0x0000000c
#define regk_gio_intr_pd8                         0x0000000d
#define regk_gio_intr_pd9                         0x0000000d
#define regk_gio_lo                               0x00000002
#define regk_gio_lsb                              0x00000000
#define regk_gio_msb                              0x00000001
#define regk_gio_negedge                          0x00000006
#define regk_gio_no                               0x00000000
#define regk_gio_no_switch                        0x0000003f
#define regk_gio_none                             0x00000007
#define regk_gio_off                              0x00000000
#define regk_gio_opendrain                        0x00000000
#define regk_gio_out                              0x00000001
#define regk_gio_posedge                          0x00000005
#define regk_gio_pwm_hfp                          0x00000002
#define regk_gio_pwm_pa0                          0x00000001
#define regk_gio_pwm_pa19                         0x00000004
#define regk_gio_pwm_pa6                          0x00000002
#define regk_gio_pwm_pa7                          0x00000003
#define regk_gio_pwm_pb26                         0x00000005
#define regk_gio_pwm_pd23                         0x00000006
#define regk_gio_pwm_pd31                         0x00000007
#define regk_gio_pwm_std                          0x00000001
#define regk_gio_pwm_var                          0x00000003
#define regk_gio_rw_i2c0_cfg_default              0x00000020
#define regk_gio_rw_i2c0_ctrl_default             0x00010000
#define regk_gio_rw_i2c0_start_default            0x00000000
#define regk_gio_rw_i2c1_cfg_default              0x00000aa0
#define regk_gio_rw_i2c1_ctrl_default             0x00010000
#define regk_gio_rw_i2c1_start_default            0x00000000
#define regk_gio_rw_intr_cfg_default              0x00000000
#define regk_gio_rw_intr_mask_default             0x00000000
#define regk_gio_rw_pa_oe_default                 0x00000000
#define regk_gio_rw_pb_oe_default                 0x00000000
#define regk_gio_rw_pc_oe_default                 0x00000000
#define regk_gio_rw_ppwm_data_default             0x00000000
#define regk_gio_rw_pwm0_ctrl_default             0x00000000
#define regk_gio_rw_pwm1_ctrl_default             0x00000000
#define regk_gio_rw_pwm2_ctrl_default             0x00000000
#define regk_gio_rw_pwm_in_cfg_default            0x00000000
#define regk_gio_sda0                             0x00000000
#define regk_gio_sda1                             0x00000001
#define regk_gio_sda2                             0x00000002
#define regk_gio_sda3                             0x00000003
#define regk_gio_sen                              0x00000000
#define regk_gio_set                              0x00000003
#define regk_gio_yes                              0x00000001
#endif /* __gio_defs_asm_h */