#
# [31mCONFIG_MN10300[0m CPU cache options
#
choice
prompt "CPU Caching mode"
default [31mCONFIG_MN10300_CACHE_WBACK[0m
help
This option determines the caching mode for the kernel.
Write-Back caching mode involves the all reads and writes causing
the affected cacheline to be read into the cache first before being
operated upon. Memory is not then updated by a write until the cache
is filled and a cacheline needs to be displaced from the cache to
make room. Only at that point is it written back.
Write-Through caching only fetches cachelines from memory on a
read. Writes always get written directly to memory. If the affected
cacheline is also in cache, it will be updated too.
The final option is to turn of caching entirely.
config [31mCONFIG_MN10300_CACHE_WBACK[0m
bool "Write-Back"
help
The dcache operates in delayed write-back mode. It must be manually
flushed if writes are made that subsequently need to be executed or
to be DMA'd by a device.
config [31mCONFIG_MN10300_CACHE_WTHRU[0m
bool "Write-Through"
help
The dcache operates in immediate write-through mode. Writes are
committed to RAM immediately in addition to being stored in the
cache. This means that the written data is immediately available for
execution or DMA.
This is not available for use with an [31mCONFIG_SMP[0m kernel if cache flushing
and invalidation by automatic purge register is not selected.
config [31mCONFIG_MN10300_CACHE_DISABLED[0m
bool "Disabled"
help
The icache and dcache are disabled.
endchoice
config [31mCONFIG_MN10300_CACHE_ENABLED[0m
def_bool y if ![31mCONFIG_MN10300_CACHE_DISABLED[0m
choice
prompt "CPU cache flush/invalidate method"
default [31mCONFIG_MN10300_CACHE_MANAGE_BY_TAG[0m if ![31mCONFIG_AM34_2[0m
default [31mCONFIG_MN10300_CACHE_MANAGE_BY_REG[0m if [31mCONFIG_AM34_2[0m
depends on [31mCONFIG_MN10300_CACHE_ENABLED[0m
help
This determines the method by which CPU cache flushing and
invalidation is performed.
config [31mCONFIG_MN10300_CACHE_MANAGE_BY_TAG[0m
bool "Use the cache tag registers directly"
depends on !([31mCONFIG_SMP[0m && [31mCONFIG_MN10300_CACHE_WTHRU[0m)
config [31mCONFIG_MN10300_CACHE_MANAGE_BY_REG[0m
bool "Flush areas by way of automatic purge registers (AM34 only)"
depends on [31mCONFIG_AM34_2[0m
endchoice
config [31mCONFIG_MN10300_CACHE_INV_BY_TAG[0m
def_bool y if [31mCONFIG_MN10300_CACHE_MANAGE_BY_TAG[0m && [31mCONFIG_MN10300_CACHE_ENABLED[0m
config [31mCONFIG_MN10300_CACHE_INV_BY_REG[0m
def_bool y if [31mCONFIG_MN10300_CACHE_MANAGE_BY_REG[0m && [31mCONFIG_MN10300_CACHE_ENABLED[0m
config [31mCONFIG_MN10300_CACHE_FLUSH_BY_TAG[0m
def_bool y if [31mCONFIG_MN10300_CACHE_MANAGE_BY_TAG[0m && [31mCONFIG_MN10300_CACHE_WBACK[0m
config [31mCONFIG_MN10300_CACHE_FLUSH_BY_REG[0m
def_bool y if [31mCONFIG_MN10300_CACHE_MANAGE_BY_REG[0m && [31mCONFIG_MN10300_CACHE_WBACK[0m
config [31mCONFIG_MN10300_HAS_CACHE_SNOOP[0m
def_bool n
config [31mCONFIG_MN10300_CACHE_SNOOP[0m
bool "Use CPU Cache Snooping"
depends on [31mCONFIG_MN10300_CACHE_ENABLED[0m && [31mCONFIG_MN10300_HAS_CACHE_SNOOP[0m
default y
config [31mCONFIG_MN10300_CACHE_FLUSH_ICACHE[0m
def_bool y if [31mCONFIG_MN10300_CACHE_WBACK[0m && ![31mCONFIG_MN10300_CACHE_SNOOP[0m
help
Set if we need the dcache flushing before the icache is invalidated.
config [31mCONFIG_MN10300_CACHE_INV_ICACHE[0m
def_bool y if [31mCONFIG_MN10300_CACHE_WTHRU[0m && ![31mCONFIG_MN10300_CACHE_SNOOP[0m
help
Set if we need the icache to be invalidated, even if the dcache is in
write-through mode and doesn't need flushing.
#
# The kernel debugger gets its own separate cache flushing functions
#
config [31mCONFIG_MN10300_DEBUGGER_CACHE_FLUSH_BY_TAG[0m
def_bool y if [31mCONFIG_KERNEL_DEBUGGER[0m && \
[31mCONFIG_MN10300_CACHE_WBACK[0m && \
![31mCONFIG_MN10300_CACHE_SNOOP[0m && \
[31mCONFIG_MN10300_CACHE_MANAGE_BY_TAG[0m
help
Set if the debugger needs to flush the dcache and invalidate the
icache using the cache tag registers to make breakpoints work.
config [31mCONFIG_MN10300_DEBUGGER_CACHE_FLUSH_BY_REG[0m
def_bool y if [31mCONFIG_KERNEL_DEBUGGER[0m && \
[31mCONFIG_MN10300_CACHE_WBACK[0m && \
![31mCONFIG_MN10300_CACHE_SNOOP[0m && \
[31mCONFIG_MN10300_CACHE_MANAGE_BY_REG[0m
help
Set if the debugger needs to flush the dcache and invalidate the
icache using automatic purge registers to make breakpoints work.
config [31mCONFIG_MN10300_DEBUGGER_CACHE_INV_BY_TAG[0m
def_bool y if [31mCONFIG_KERNEL_DEBUGGER[0m && \
[31mCONFIG_MN10300_CACHE_WTHRU[0m && \
![31mCONFIG_MN10300_CACHE_SNOOP[0m && \
[31mCONFIG_MN10300_CACHE_MANAGE_BY_TAG[0m
help
Set if the debugger needs to invalidate the icache using the cache
tag registers to make breakpoints work.
config [31mCONFIG_MN10300_DEBUGGER_CACHE_INV_BY_REG[0m
def_bool y if [31mCONFIG_KERNEL_DEBUGGER[0m && \
[31mCONFIG_MN10300_CACHE_WTHRU[0m && \
![31mCONFIG_MN10300_CACHE_SNOOP[0m && \
[31mCONFIG_MN10300_CACHE_MANAGE_BY_REG[0m
help
Set if the debugger needs to invalidate the icache using automatic
purge registers to make breakpoints work.
config [31mCONFIG_MN10300_DEBUGGER_CACHE_NO_FLUSH[0m
def_bool y if [31mCONFIG_KERNEL_DEBUGGER[0m && \
([31mCONFIG_MN10300_CACHE_DISABLED[0m || [31mCONFIG_MN10300_CACHE_SNOOP[0m)
help
Set if the debugger does not need to flush the dcache and/or
invalidate the icache to make breakpoints work.