#
# Renesas SH and SH Mobile [31mCONFIG_PINCTRL[0m drivers
#
if [31mCONFIG_ARCH_RENESAS[0m || [31mCONFIG_SUPERH[0m
config [31mCONFIG_PINCTRL_SH_PFC[0m
select [31mCONFIG_PINMUX[0m
select [31mCONFIG_PINCONF[0m
select [31mCONFIG_GENERIC_PINCONF[0m
def_bool y
help
This enables pin control drivers for SH and SH Mobile platforms
config [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_PINCTRL_SH_PFC[0m
bool
help
This enables pin control and GPIO drivers for SH/SH Mobile platforms
config [31mCONFIG_PINCTRL_PFC_EMEV2[0m
def_bool y
depends on [31mCONFIG_ARCH_EMEV2[0m
select [31mCONFIG_PINCTRL_SH_PFC[0m
config [31mCONFIG_PINCTRL_PFC_R8A73A4[0m
def_bool y
depends on [31mCONFIG_ARCH_R8A73A4[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
config [31mCONFIG_PINCTRL_PFC_R8A7740[0m
def_bool y
depends on [31mCONFIG_ARCH_R8A7740[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
config [31mCONFIG_PINCTRL_PFC_R8A7778[0m
def_bool y
depends on [31mCONFIG_ARCH_R8A7778[0m
select [31mCONFIG_PINCTRL_SH_PFC[0m
config [31mCONFIG_PINCTRL_PFC_R8A7779[0m
def_bool y
depends on [31mCONFIG_ARCH_R8A7779[0m
select [31mCONFIG_PINCTRL_SH_PFC[0m
config [31mCONFIG_PINCTRL_PFC_R8A7790[0m
def_bool y
depends on [31mCONFIG_ARCH_R8A7790[0m
select [31mCONFIG_PINCTRL_SH_PFC[0m
config [31mCONFIG_PINCTRL_PFC_R8A7791[0m
def_bool y
depends on [31mCONFIG_ARCH_R8A7791[0m
select [31mCONFIG_PINCTRL_SH_PFC[0m
config [31mCONFIG_PINCTRL_PFC_R8A7792[0m
def_bool y
depends on [31mCONFIG_ARCH_R8A7792[0m
select [31mCONFIG_PINCTRL_SH_PFC[0m
config [31mCONFIG_PINCTRL_PFC_R8A7793[0m
def_bool y
depends on [31mCONFIG_ARCH_R8A7793[0m
select [31mCONFIG_PINCTRL_SH_PFC[0m
config [31mCONFIG_PINCTRL_PFC_R8A7794[0m
def_bool y
depends on [31mCONFIG_ARCH_R8A7794[0m
select [31mCONFIG_PINCTRL_SH_PFC[0m
config [31mCONFIG_PINCTRL_PFC_R8A7795[0m
def_bool y
depends on [31mCONFIG_ARCH_R8A7795[0m
select [31mCONFIG_PINCTRL_SH_PFC[0m
config [31mCONFIG_PINCTRL_PFC_R8A7796[0m
def_bool y
depends on [31mCONFIG_ARCH_R8A7796[0m
select [31mCONFIG_PINCTRL_SH_PFC[0m
config [31mCONFIG_PINCTRL_PFC_SH7203[0m
def_bool y
depends on [31mCONFIG_CPU_SUBTYPE_SH7203[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
config [31mCONFIG_PINCTRL_PFC_SH7264[0m
def_bool y
depends on [31mCONFIG_CPU_SUBTYPE_SH7264[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
config [31mCONFIG_PINCTRL_PFC_SH7269[0m
def_bool y
depends on [31mCONFIG_CPU_SUBTYPE_SH7269[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
config [31mCONFIG_PINCTRL_PFC_SH73A0[0m
def_bool y
depends on [31mCONFIG_ARCH_SH73A0[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
select [31mCONFIG_REGULATOR[0m
config [31mCONFIG_PINCTRL_PFC_SH7720[0m
def_bool y
depends on [31mCONFIG_CPU_SUBTYPE_SH7720[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
config [31mCONFIG_PINCTRL_PFC_SH7722[0m
def_bool y
depends on [31mCONFIG_CPU_SUBTYPE_SH7722[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
config [31mCONFIG_PINCTRL_PFC_SH7723[0m
def_bool y
depends on [31mCONFIG_CPU_SUBTYPE_SH7723[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
config [31mCONFIG_PINCTRL_PFC_SH7724[0m
def_bool y
depends on [31mCONFIG_CPU_SUBTYPE_SH7724[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
config [31mCONFIG_PINCTRL_PFC_SH7734[0m
def_bool y
depends on [31mCONFIG_CPU_SUBTYPE_SH7734[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
config [31mCONFIG_PINCTRL_PFC_SH7757[0m
def_bool y
depends on [31mCONFIG_CPU_SUBTYPE_SH7757[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
config [31mCONFIG_PINCTRL_PFC_SH7785[0m
def_bool y
depends on [31mCONFIG_CPU_SUBTYPE_SH7785[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
config [31mCONFIG_PINCTRL_PFC_SH7786[0m
def_bool y
depends on [31mCONFIG_CPU_SUBTYPE_SH7786[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
config [31mCONFIG_PINCTRL_PFC_SHX3[0m
def_bool y
depends on [31mCONFIG_CPU_SUBTYPE_SHX3[0m
select [31mCONFIG_PINCTRL_SH_PFC_GPIO[0m
endif