if [31mCONFIG_ETRAX_ARCH_V10[0m
config [31mCONFIG_ETRAX_ETHERNET[0m
bool "Ethernet support"
depends on [31mCONFIG_ETRAX_ARCH_V10[0m && [31mCONFIG_NETDEVICES[0m
select [31mCONFIG_MII[0m
help
This option enables the ETRAX 100LX built-in 10/100Mbit Ethernet
controller.
config [31mCONFIG_ETRAX_SERIAL[0m
bool "Serial-port support"
depends on [31mCONFIG_ETRAX_ARCH_V10[0m
help
Enables the ETRAX 100 serial driver for ser0 (ttyS0)
You probably want this enabled.
config [31mCONFIG_ETRAX_SERIAL_FAST_TIMER[0m
bool "Use fast timers for serial DMA flush (experimental)"
depends on [31mCONFIG_ETRAX_SERIAL[0m
help
Select this to have the serial DMAs flushed at a higher rate than
normally, possible by using the fast timer API, the timeout is
approx. 4 character times.
If unsure, say N.
config [31mCONFIG_ETRAX_SERIAL_FLUSH_DMA_FAST[0m
bool "Fast serial port DMA flush"
depends on [31mCONFIG_ETRAX_SERIAL[0m && ![31mCONFIG_ETRAX_SERIAL_FAST_TIMER[0m
help
Select this to have the serial DMAs flushed at a higher rate than
normally possible through a fast timer interrupt (currently at
15360 Hz).
If unsure, say N.
config [31mCONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS[0m
int "Receive flush timeout (ticks) "
depends on [31mCONFIG_ETRAX_SERIAL[0m && ![31mCONFIG_ETRAX_SERIAL_FAST_TIMER[0m && ![31mCONFIG_ETRAX_SERIAL_FLUSH_DMA_FAST[0m
default "5"
help
Number of timer ticks between flush of receive fifo (1 tick = 10ms).
Try 0-3 for low latency applications. Approx 5 for high load
applications (e.g. [31mCONFIG_PPP[0m). Maybe this should be more adaptive some
day...
config [31mCONFIG_ETRAX_SERIAL_PORT0[0m
bool "Serial port 0 enabled"
depends on [31mCONFIG_ETRAX_SERIAL[0m
help
Enables the ETRAX 100 serial driver for ser0 (ttyS0)
Normally you want this on, unless you use external DMA 1 that uses
the same DMA channels.
choice
prompt "Ser0 DTR, RI, DSR and CD assignment"
depends on [31mCONFIG_ETRAX_SERIAL_PORT0[0m
default [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE[0m
config [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE[0m
bool "No_DTR_RI_DSR_CD"
config [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA[0m
bool "DTR_RI_DSR_CD_on_PA"
config [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB[0m
bool "DTR_RI_DSR_CD_on_PB"
help
Enables the status and control signals DTR, RI, DSR and CD on PB for
ser0.
config [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
endchoice
config [31mCONFIG_ETRAX_SER0_DTR_ON_PA_BIT[0m
int "Ser0 DTR on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT0[0m
default "-1" if ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA[0m && ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
default "4" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
config [31mCONFIG_ETRAX_SER0_RI_ON_PA_BIT[0m
int "Ser0 RI on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT0[0m
default "-1" if ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA[0m && ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
default "5" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
config [31mCONFIG_ETRAX_SER0_DSR_ON_PA_BIT[0m
int "Ser0 DSR on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT0[0m
default "-1" if ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA[0m && ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
default "6" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
config [31mCONFIG_ETRAX_SER0_CD_ON_PA_BIT[0m
int "Ser0 CD on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT0[0m
default "-1" if ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA[0m && ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
default "7" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
config [31mCONFIG_ETRAX_SER0_DTR_ON_PB_BIT[0m
int "Ser0 DTR on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT0[0m
default "-1" if ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB[0m && ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
default "4" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
help
Specify the pin of the PB port to carry the DTR signal for serial
port 0.
config [31mCONFIG_ETRAX_SER0_RI_ON_PB_BIT[0m
int "Ser0 RI on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT0[0m
default "-1" if ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB[0m && ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
default "5" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
help
Specify the pin of the PB port to carry the RI signal for serial
port 0.
config [31mCONFIG_ETRAX_SER0_DSR_ON_PB_BIT[0m
int "Ser0 DSR on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT0[0m
default "-1" if ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB[0m && ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
default "6" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
help
Specify the pin of the PB port to carry the DSR signal for serial
port 0.
config [31mCONFIG_ETRAX_SER0_CD_ON_PB_BIT[0m
int "Ser0 CD on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT0[0m
default "-1" if ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB[0m && ![31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
default "7" if [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED[0m
help
Specify the pin of the PB port to carry the CD signal for serial
port 0.
config [31mCONFIG_ETRAX_SERIAL_PORT1[0m
bool "Serial port 1 enabled"
depends on [31mCONFIG_ETRAX_SERIAL[0m
help
Enables the ETRAX 100 serial driver for ser1 (ttyS1).
choice
prompt "Ser1 DTR, RI, DSR and CD assignment"
depends on [31mCONFIG_ETRAX_SERIAL_PORT1[0m
default [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE[0m
config [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE[0m
bool "No_DTR_RI_DSR_CD"
config [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PA[0m
bool "DTR_RI_DSR_CD_on_PA"
config [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB[0m
bool "DTR_RI_DSR_CD_on_PB"
help
Enables the status and control signals DTR, RI, DSR and CD on PB for
ser1.
config [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
endchoice
config [31mCONFIG_ETRAX_SER1_DTR_ON_PA_BIT[0m
int "Ser1 DTR on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT1[0m
default "-1" if ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PA[0m && ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
default "4" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
config [31mCONFIG_ETRAX_SER1_RI_ON_PA_BIT[0m
int "Ser1 RI on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT1[0m
default "-1" if ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PA[0m && ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
default "5" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
config [31mCONFIG_ETRAX_SER1_DSR_ON_PA_BIT[0m
int "Ser1 DSR on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT1[0m
default "-1" if ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PA[0m && ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
default "6" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
config [31mCONFIG_ETRAX_SER1_CD_ON_PA_BIT[0m
int "Ser1 CD on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT1[0m
default "-1" if ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PA[0m && ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
default "7" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
config [31mCONFIG_ETRAX_SER1_DTR_ON_PB_BIT[0m
int "Ser1 DTR on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT1[0m
default "-1" if ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB[0m && ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
default "4" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
help
Specify the pin of the PB port to carry the DTR signal for serial
port 1.
config [31mCONFIG_ETRAX_SER1_RI_ON_PB_BIT[0m
int "Ser1 RI on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT1[0m
default "-1" if ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB[0m && ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
default "5" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
help
Specify the pin of the PB port to carry the RI signal for serial
port 1.
config [31mCONFIG_ETRAX_SER1_DSR_ON_PB_BIT[0m
int "Ser1 DSR on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT1[0m
default "-1" if ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB[0m && ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
default "6" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
help
Specify the pin of the PB port to carry the DSR signal for serial
port 1.
config [31mCONFIG_ETRAX_SER1_CD_ON_PB_BIT[0m
int "Ser1 CD on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT1[0m
default "-1" if ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB[0m && ![31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
default "7" if [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED[0m
help
Specify the pin of the PB port to carry the CD signal for serial
port 1.
comment "Make sure you do not have the same PB bits more than once!"
depends on [31mCONFIG_ETRAX_SERIAL[0m && [31mCONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB[0m && [31mCONFIG_ETRAX_SER1_DTR_RI_DSR_CD_ON_PB[0m
config [31mCONFIG_ETRAX_SERIAL_PORT2[0m
bool "Serial port 2 enabled"
depends on [31mCONFIG_ETRAX_SERIAL[0m
help
Enables the ETRAX 100 serial driver for ser2 (ttyS2).
choice
prompt "Ser2 DTR, RI, DSR and CD assignment"
depends on [31mCONFIG_ETRAX_SERIAL_PORT2[0m
default [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE[0m
config [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE[0m
bool "No_DTR_RI_DSR_CD"
config [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA[0m
bool "DTR_RI_DSR_CD_on_PA"
help
Enables the status and control signals DTR, RI, DSR and CD on PA for
ser2.
config [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB[0m
bool "DTR_RI_DSR_CD_on_PB"
config [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
endchoice
config [31mCONFIG_ETRAX_SER2_DTR_ON_PA_BIT[0m
int "Ser2 DTR on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT2[0m
default "-1" if ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA[0m && ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
default "4" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
help
Specify the pin of the PA port to carry the DTR signal for serial
port 2.
config [31mCONFIG_ETRAX_SER2_RI_ON_PA_BIT[0m
int "Ser2 RI on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT2[0m
default "-1" if ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA[0m && ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
default "5" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
help
Specify the pin of the PA port to carry the RI signal for serial
port 2.
config [31mCONFIG_ETRAX_SER2_DSR_ON_PA_BIT[0m
int "Ser2 DSR on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT2[0m
default "-1" if ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA[0m && ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
default "6" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
help
Specify the pin of the PA port to carry the DTR signal for serial
port 2.
config [31mCONFIG_ETRAX_SER2_CD_ON_PA_BIT[0m
int "Ser2 CD on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT2[0m
default "-1" if ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA[0m && ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
default "7" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
help
Specify the pin of the PA port to carry the CD signal for serial
port 2.
config [31mCONFIG_ETRAX_SER2_DTR_ON_PB_BIT[0m
int "Ser2 DTR on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT2[0m
default "-1" if ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB[0m && ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
default "4" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
config [31mCONFIG_ETRAX_SER2_RI_ON_PB_BIT[0m
int "Ser2 RI on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT2[0m
default "-1" if ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB[0m && ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
default "5" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
config [31mCONFIG_ETRAX_SER2_DSR_ON_PB_BIT[0m
int "Ser2 DSR on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT2[0m
default "-1" if ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB[0m && ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
default "6" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
config [31mCONFIG_ETRAX_SER2_CD_ON_PB_BIT[0m
int "Ser2 CD on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT2[0m
default "-1" if ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB[0m && ![31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
default "7" if [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED[0m
config [31mCONFIG_ETRAX_SERIAL_PORT3[0m
bool "Serial port 3 enabled"
depends on [31mCONFIG_ETRAX_SERIAL[0m
help
Enables the ETRAX 100 serial driver for ser3 (ttyS3).
choice
prompt "Ser3 DTR, RI, DSR and CD assignment"
depends on [31mCONFIG_ETRAX_SERIAL_PORT3[0m
default [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE[0m
config [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE[0m
bool "No_DTR_RI_DSR_CD"
config [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_ON_PA[0m
bool "DTR_RI_DSR_CD_on_PA"
config [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_ON_PB[0m
bool "DTR_RI_DSR_CD_on_PB"
config [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED[0m
bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
endchoice
config [31mCONFIG_ETRAX_SER3_DTR_ON_PA_BIT[0m
int "Ser3 DTR on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT3[0m
default "-1"
config [31mCONFIG_ETRAX_SER3_RI_ON_PA_BIT[0m
int "Ser3 RI on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT3[0m
default "-1"
config [31mCONFIG_ETRAX_SER3_DSR_ON_PA_BIT[0m
int "Ser3 DSR on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT3[0m
default "-1"
config [31mCONFIG_ETRAX_SER3_CD_ON_PA_BIT[0m
int "Ser3 CD on PA bit (-1 = not used)" if [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_ON_PA[0m || [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT3[0m
default "-1"
config [31mCONFIG_ETRAX_SER3_DTR_ON_PB_BIT[0m
int "Ser3 DTR on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT3[0m
default "-1"
config [31mCONFIG_ETRAX_SER3_RI_ON_PB_BIT[0m
int "Ser3 RI on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT3[0m
default "-1"
config [31mCONFIG_ETRAX_SER3_DSR_ON_PB_BIT[0m
int "Ser3 DSR on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT3[0m
default "-1"
config [31mCONFIG_ETRAX_SER3_CD_ON_PB_BIT[0m
int "Ser3 CD on PB bit (-1 = not used)" if [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_ON_PB[0m || [31mCONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED[0m
depends on [31mCONFIG_ETRAX_SERIAL_PORT3[0m
default "-1"
config [31mCONFIG_ETRAX_RS485[0m
bool "RS-485 support"
depends on [31mCONFIG_ETRAX_SERIAL[0m
help
Enables support for RS-485 serial communication. For a primer on
RS-485, see <http://en.wikipedia.org/wiki/Rs485>
config [31mCONFIG_ETRAX_RS485_ON_PA[0m
bool "RS-485 mode on PA"
depends on [31mCONFIG_ETRAX_RS485[0m
help
Control Driver Output Enable on RS485 transceiver using a pin on PA
port:
Axis 2400/2401 uses PA 3.
config [31mCONFIG_ETRAX_RS485_ON_PA_BIT[0m
int "RS-485 mode on PA bit"
depends on [31mCONFIG_ETRAX_RS485_ON_PA[0m
default "3"
help
Control Driver Output Enable on RS485 transceiver using a this bit
on PA port.
config [31mCONFIG_ETRAX_RS485_DISABLE_RECEIVER[0m
bool "Disable serial receiver"
depends on [31mCONFIG_ETRAX_RS485[0m
help
It's necessary to disable the serial receiver to avoid serial
loopback. Not all products are able to do this in software only.
Axis 2400/2401 must disable receiver.
config [31mCONFIG_ETRAX_USB_HOST[0m
bool "USB host"
select [31mCONFIG_USB[0m
help
This option enables the host functionality of the ETRAX 100LX
built-in [31mCONFIG_USB[0m controller. In host mode the controller is designed
for CTRL and BULK traffic only, INTR traffic may work as well
however (depending on the requirements of timeliness).
config [31mCONFIG_ETRAX_PTABLE_SECTOR[0m
int "Byte-offset of partition table sector"
depends on [31mCONFIG_ETRAX_AXISFLASHMAP[0m
default "65536"
help
Byte-offset of the partition table in the first flash chip.
The default value is 64kB and should not be changed unless
you know exactly what you are doing. The only valid reason
for changing this is when the flash block size is bigger
than 64kB (e.g. when using two parallel 16 bit flashes).
config [31mCONFIG_ETRAX_I2C[0m
bool "I2C support"
depends on [31mCONFIG_ETRAX_ARCH_V10[0m
help
Enables an [31mCONFIG_I2C[0m driver on ETRAX100.
EXAMPLE usage:
i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val);
ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg);
i2c_arg = I2C_READARG(STA013_READ_ADDR, reg);
val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg);
# this is true for most products since PB-[31mCONFIG_I2C[0m seems to be somewhat
# flawed..
config [31mCONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C[0m
bool "I2C uses PB not PB-I2C"
depends on [31mCONFIG_ETRAX_I2C[0m
help
Select whether to use the special [31mCONFIG_I2C[0m mode in the PB I/O register or
not. This option needs to be selected in order to use some drivers
that access the [31mCONFIG_I2C[0m I/O pins directly instead of going through the
[31mCONFIG_I2C[0m driver, like the [31mCONFIG_DS1302[0m realtime-clock driver. If you are
uncertain, choose Y here.
config [31mCONFIG_ETRAX_I2C_DATA_PORT[0m
int "I2C SDA bit number"
depends on [31mCONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C[0m
default "0"
help
Selects the pin on Port [31mCONFIG_B[0m where the data pin is connected
config [31mCONFIG_ETRAX_I2C_CLK_PORT[0m
int "I2C SCL bit number"
depends on [31mCONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C[0m
default "1"
help
Select the pin on Port [31mCONFIG_B[0m where the clock pin is connected
config [31mCONFIG_ETRAX_I2C_EEPROM[0m
bool "I2C EEPROM (non-volatile RAM) support"
depends on [31mCONFIG_ETRAX_I2C[0m
help
Enables [31mCONFIG_I2C[0m EEPROM (non-volatile RAM) on PB0 and PB1 using the [31mCONFIG_I2C[0m
driver. Select size option: Probed, 2k, 8k, 16k.
(Probing works for 2k and 8k but not that well for 16k)
choice
prompt "EEPROM size"
depends on [31mCONFIG_ETRAX_I2C_EEPROM[0m
default [31mCONFIG_ETRAX_I2C_EEPROM_PROBE[0m
config [31mCONFIG_ETRAX_I2C_EEPROM_PROBE[0m
bool "Probed"
help
Specifies size or auto probe of the EEPROM size.
Options: Probed, 2k, 8k, 16k.
(Probing works for 2k and 8k but not that well for 16k)
config [31mCONFIG_ETRAX_I2C_EEPROM_2KB[0m
bool "2kB"
help
Use a 2kB EEPROM.
config [31mCONFIG_ETRAX_I2C_EEPROM_8KB[0m
bool "8kB"
help
Use a 8kB EEPROM.
config [31mCONFIG_ETRAX_I2C_EEPROM_16KB[0m
bool "16kB"
help
Use a 16kB EEPROM.
endchoice
config [31mCONFIG_ETRAX_GPIO[0m
bool "GPIO support"
depends on [31mCONFIG_ETRAX_ARCH_V10[0m
---help---
Enables the ETRAX general port device (major 120, minors 0 and 1).
You can use this driver to access the general port bits. It supports
these ioctl's:
#include <linux/etraxgpio.h>
fd = open("/dev/gpioa", O_RDWR); // or /dev/gpiob
ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_SETBITS), bits_to_set);
ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_CLRBITS), bits_to_clear);
val = ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_READBITS), NULL);
Remember that you need to setup the port directions appropriately in
the General configuration.
config [31mCONFIG_ETRAX_PA_CHANGEABLE_DIR[0m
hex "PA user changeable dir mask"
depends on [31mCONFIG_ETRAX_GPIO[0m
default "00"
help
This is a bitmask with information of what bits in PA that a user
can change direction on using ioctl's.
Bit set = changeable.
You probably want 00 here.
config [31mCONFIG_ETRAX_PA_CHANGEABLE_BITS[0m
hex "PA user changeable bits mask"
depends on [31mCONFIG_ETRAX_GPIO[0m
default "FF"
help
This is a bitmask with information of what bits in PA that a user
can change the value on using ioctl's.
Bit set = changeable.
You probably want 00 here.
config [31mCONFIG_ETRAX_PB_CHANGEABLE_DIR[0m
hex "PB user changeable dir mask"
depends on [31mCONFIG_ETRAX_GPIO[0m
default "00"
help
This is a bitmask with information of what bits in PB that a user
can change direction on using ioctl's.
Bit set = changeable.
You probably want 00 here.
config [31mCONFIG_ETRAX_PB_CHANGEABLE_BITS[0m
hex "PB user changeable bits mask"
depends on [31mCONFIG_ETRAX_GPIO[0m
default "FF"
help
This is a bitmask with information of what bits in PB that a user
can change the value on using ioctl's.
Bit set = changeable.
You probably want 00 here.
endif