1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 | /* * Winbond W6692 specific defines * * Author Karsten Keil <keil@isdn4linux.de> * based on the w6692 I4L driver from Petr Novak <petr.novak@i.cz> * * Copyright 2009 by Karsten Keil <keil@isdn4linux.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * */ /* Specifications of W6692 registers */ #define W_D_RFIFO 0x00 /* R */ #define W_D_XFIFO 0x04 /* W */ #define W_D_CMDR 0x08 /* W */ #define W_D_MODE 0x0c /* R/W */ #define W_D_TIMR 0x10 /* R/W */ #define W_ISTA 0x14 /* R_clr */ #define W_IMASK 0x18 /* R/W */ #define W_D_EXIR 0x1c /* R_clr */ #define W_D_EXIM 0x20 /* R/W */ #define W_D_STAR 0x24 /* R */ #define W_D_RSTA 0x28 /* R */ #define W_D_SAM 0x2c /* R/W */ #define W_D_SAP1 0x30 /* R/W */ #define W_D_SAP2 0x34 /* R/W */ #define W_D_TAM 0x38 /* R/W */ #define W_D_TEI1 0x3c /* R/W */ #define W_D_TEI2 0x40 /* R/W */ #define W_D_RBCH 0x44 /* R */ #define W_D_RBCL 0x48 /* R */ #define W_TIMR2 0x4c /* W */ #define W_L1_RC 0x50 /* R/W */ #define W_D_CTL 0x54 /* R/W */ #define W_CIR 0x58 /* R */ #define W_CIX 0x5c /* W */ #define W_SQR 0x60 /* R */ #define W_SQX 0x64 /* W */ #define W_PCTL 0x68 /* R/W */ #define W_MOR 0x6c /* R */ #define W_MOX 0x70 /* R/W */ #define W_MOSR 0x74 /* R_clr */ #define W_MOCR 0x78 /* R/W */ #define W_GCR 0x7c /* R/W */ #define W_B_RFIFO 0x80 /* R */ #define W_B_XFIFO 0x84 /* W */ #define W_B_CMDR 0x88 /* W */ #define W_B_MODE 0x8c /* R/W */ #define W_B_EXIR 0x90 /* R_clr */ #define W_B_EXIM 0x94 /* R/W */ #define W_B_STAR 0x98 /* R */ #define W_B_ADM1 0x9c /* R/W */ #define W_B_ADM2 0xa0 /* R/W */ #define W_B_ADR1 0xa4 /* R/W */ #define W_B_ADR2 0xa8 /* R/W */ #define W_B_RBCL 0xac /* R */ #define W_B_RBCH 0xb0 /* R */ #define W_XADDR 0xf4 /* R/W */ #define W_XDATA 0xf8 /* R/W */ #define W_EPCTL 0xfc /* W */ /* W6692 register bits */ #define W_D_CMDR_XRST 0x01 #define W_D_CMDR_XME 0x02 #define W_D_CMDR_XMS 0x08 #define W_D_CMDR_STT 0x10 #define W_D_CMDR_RRST 0x40 #define W_D_CMDR_RACK 0x80 #define W_D_MODE_RLP 0x01 #define W_D_MODE_DLP 0x02 #define W_D_MODE_MFD 0x04 #define W_D_MODE_TEE 0x08 #define W_D_MODE_TMS 0x10 #define W_D_MODE_RACT 0x40 #define W_D_MODE_MMS 0x80 #define W_INT_B2_EXI 0x01 #define W_INT_B1_EXI 0x02 #define W_INT_D_EXI 0x04 #define W_INT_XINT0 0x08 #define W_INT_XINT1 0x10 #define W_INT_D_XFR 0x20 #define W_INT_D_RME 0x40 #define W_INT_D_RMR 0x80 #define W_D_EXI_WEXP 0x01 #define W_D_EXI_TEXP 0x02 #define W_D_EXI_ISC 0x04 #define W_D_EXI_MOC 0x08 #define W_D_EXI_TIN2 0x10 #define W_D_EXI_XCOL 0x20 #define W_D_EXI_XDUN 0x40 #define W_D_EXI_RDOV 0x80 #define W_D_STAR_DRDY 0x10 #define W_D_STAR_XBZ 0x20 #define W_D_STAR_XDOW 0x80 #define W_D_RSTA_RMB 0x10 #define W_D_RSTA_CRCE 0x20 #define W_D_RSTA_RDOV 0x40 #define W_D_CTL_SRST 0x20 #define W_CIR_SCC 0x80 #define W_CIR_ICC 0x40 #define W_CIR_COD_MASK 0x0f #define W_PCTL_PCX 0x01 #define W_PCTL_XMODE 0x02 #define W_PCTL_OE0 0x04 #define W_PCTL_OE1 0x08 #define W_PCTL_OE2 0x10 #define W_PCTL_OE3 0x20 #define W_PCTL_OE4 0x40 #define W_PCTL_OE5 0x80 #define W_B_CMDR_XRST 0x01 #define W_B_CMDR_XME 0x02 #define W_B_CMDR_XMS 0x04 #define W_B_CMDR_RACT 0x20 #define W_B_CMDR_RRST 0x40 #define W_B_CMDR_RACK 0x80 #define W_B_MODE_FTS0 0x01 #define W_B_MODE_FTS1 0x02 #define W_B_MODE_SW56 0x04 #define W_B_MODE_BSW0 0x08 #define W_B_MODE_BSW1 0x10 #define W_B_MODE_EPCM 0x20 #define W_B_MODE_ITF 0x40 #define W_B_MODE_MMS 0x80 #define W_B_EXI_XDUN 0x01 #define W_B_EXI_XFR 0x02 #define W_B_EXI_RDOV 0x10 #define W_B_EXI_RME 0x20 #define W_B_EXI_RMR 0x40 #define W_B_STAR_XBZ 0x01 #define W_B_STAR_XDOW 0x04 #define W_B_STAR_RMB 0x10 #define W_B_STAR_CRCE 0x20 #define W_B_STAR_RDOV 0x40 #define W_B_RBCH_LOV 0x20 /* W6692 Layer1 commands */ #define W_L1CMD_ECK 0x00 #define W_L1CMD_RST 0x01 #define W_L1CMD_SCP 0x04 #define W_L1CMD_SSP 0x02 #define W_L1CMD_AR8 0x08 #define W_L1CMD_AR10 0x09 #define W_L1CMD_EAL 0x0a #define W_L1CMD_DRC 0x0f /* W6692 Layer1 indications */ #define W_L1IND_CE 0x07 #define W_L1IND_DRD 0x00 #define W_L1IND_LD 0x04 #define W_L1IND_ARD 0x08 #define W_L1IND_TI 0x0a #define W_L1IND_ATI 0x0b #define W_L1IND_AI8 0x0c #define W_L1IND_AI10 0x0d #define W_L1IND_CD 0x0f /* FIFO thresholds */ #define W_D_FIFO_THRESH 64 #define W_B_FIFO_THRESH 64 |