1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 | /* * Blackfin CPLB initialization * * Copyright 2007-2009 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ #include <linux/module.h> #include <asm/blackfin.h> #include <asm/cacheflush.h> #include <asm/cplb.h> #include <asm/cplbinit.h> #include <asm/mem_map.h> struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR; struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR; int first_switched_icplb PDT_ATTR; int first_switched_dcplb PDT_ATTR; struct cplb_boundary dcplb_bounds[9] PDT_ATTR; struct cplb_boundary icplb_bounds[9] PDT_ATTR; int icplb_nr_bounds PDT_ATTR; int dcplb_nr_bounds PDT_ATTR; void __init generate_cplb_tables_cpu(unsigned int cpu) { int i_d, i_i; unsigned long addr; unsigned long cplb_pageflags, cplb_pagesize; struct cplb_entry *d_tbl = dcplb_tbl[cpu]; struct cplb_entry *i_tbl = icplb_tbl[cpu]; printk(KERN_INFO "NOMPU: setting up cplb tables\n"); i_d = i_i = 0; #ifdef [31mCONFIG_DEBUG_HUNT_FOR_ZERO[0m /* Set up the zero page. */ d_tbl[i_d].addr = 0; d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; i_tbl[i_i].addr = 0; i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB; #endif /* Cover kernel memory with 4M pages. */ addr = 0; #ifdef PAGE_SIZE_16MB cplb_pageflags = PAGE_SIZE_16MB; cplb_pagesize = SIZE_16M; #else cplb_pageflags = PAGE_SIZE_4MB; cplb_pagesize = SIZE_4M; #endif for (; addr < memory_start; addr += cplb_pagesize) { d_tbl[i_d].addr = addr; d_tbl[i_d++].data = SDRAM_DGENERIC | cplb_pageflags; i_tbl[i_i].addr = addr; i_tbl[i_i++].data = SDRAM_IGENERIC | cplb_pageflags; } #ifdef [31mCONFIG_ROMKERNEL[0m /* Cover kernel XIP flash area */ #ifdef [31mCONFIG_BF60x[0m addr = [31mCONFIG_ROM_BASE[0m & ~(16 * 1024 * 1024 - 1); d_tbl[i_d].addr = addr; d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_16MB; i_tbl[i_i].addr = addr; i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_16MB; #else addr = [31mCONFIG_ROM_BASE[0m & ~(4 * 1024 * 1024 - 1); d_tbl[i_d].addr = addr; d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB; i_tbl[i_i].addr = addr; i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB; #endif #endif /* Cover L1 memory. One 4M area for code and data each is enough. */ if (cpu == 0) { if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { d_tbl[i_d].addr = L1_DATA_A_START; d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; } i_tbl[i_i].addr = L1_CODE_START; i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; } #ifdef [31mCONFIG_SMP[0m else { if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { d_tbl[i_d].addr = COREB_L1_DATA_A_START; d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; } i_tbl[i_i].addr = COREB_L1_CODE_START; i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; } #endif first_switched_dcplb = i_d; first_switched_icplb = i_i; BUG_ON(first_switched_dcplb > MAX_CPLBS); BUG_ON(first_switched_icplb > MAX_CPLBS); while (i_d < MAX_CPLBS) d_tbl[i_d++].data = 0; while (i_i < MAX_CPLBS) i_tbl[i_i++].data = 0; } void __init generate_cplb_tables_all(void) { unsigned long uncached_end; int i_d, i_i; i_d = 0; /* Normal RAM, including MTD FS. */ #ifdef [31mCONFIG_MTD_UCLINUX[0m uncached_end = memory_mtd_start + mtd_size; #else uncached_end = memory_end; #endif /* * if DMA uncached is less than 1MB, mark the 1MB chunk as uncached * so that we don't have to use 4kB pages and cause CPLB thrashing */ if ((DMA_UNCACHED_REGION >= 1 * 1024 * 1024) || !DMA_UNCACHED_REGION || ((_ramend - uncached_end) >= 1 * 1024 * 1024)) dcplb_bounds[i_d].eaddr = uncached_end; else dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1); dcplb_bounds[i_d++].data = SDRAM_DGENERIC; /* DMA uncached region. */ if (DMA_UNCACHED_REGION) { dcplb_bounds[i_d].eaddr = _ramend; dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL; } if (_ramend != physical_mem_end) { /* Reserved memory. */ dcplb_bounds[i_d].eaddr = physical_mem_end; dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ? SDRAM_DGENERIC : SDRAM_DNON_CHBL); } /* Addressing hole up to the async bank. */ dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE; dcplb_bounds[i_d++].data = 0; /* ASYNC banks. */ dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE; dcplb_bounds[i_d++].data = SDRAM_EBIU; /* Addressing hole up to BootROM. */ dcplb_bounds[i_d].eaddr = BOOT_ROM_START; dcplb_bounds[i_d++].data = 0; /* BootROM -- largest one should be less than 1 meg. */ dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH; dcplb_bounds[i_d++].data = SDRAM_DGENERIC; if (L2_LENGTH) { /* Addressing hole up to L2 SRAM. */ dcplb_bounds[i_d].eaddr = L2_START; dcplb_bounds[i_d++].data = 0; /* L2 SRAM. */ dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH; dcplb_bounds[i_d++].data = L2_DMEMORY; } dcplb_nr_bounds = i_d; BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds)); i_i = 0; /* Normal RAM, including MTD FS. */ icplb_bounds[i_i].eaddr = uncached_end; icplb_bounds[i_i++].data = SDRAM_IGENERIC; if (_ramend != physical_mem_end) { /* DMA uncached region. */ if (DMA_UNCACHED_REGION) { /* Normally this hole is caught by the async below. */ icplb_bounds[i_i].eaddr = _ramend; icplb_bounds[i_i++].data = 0; } /* Reserved memory. */ icplb_bounds[i_i].eaddr = physical_mem_end; icplb_bounds[i_i++].data = (reserved_mem_icache_on ? SDRAM_IGENERIC : SDRAM_INON_CHBL); } /* Addressing hole up to the async bank. */ icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE; icplb_bounds[i_i++].data = 0; /* ASYNC banks. */ icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE; icplb_bounds[i_i++].data = SDRAM_EBIU; /* Addressing hole up to BootROM. */ icplb_bounds[i_i].eaddr = BOOT_ROM_START; icplb_bounds[i_i++].data = 0; /* BootROM -- largest one should be less than 1 meg. */ icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH; icplb_bounds[i_i++].data = SDRAM_IGENERIC; if (L2_LENGTH) { /* Addressing hole up to L2 SRAM. */ icplb_bounds[i_i].eaddr = L2_START; icplb_bounds[i_i++].data = 0; /* L2 SRAM. */ icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH; icplb_bounds[i_i++].data = L2_IMEMORY; } icplb_nr_bounds = i_i; BUG_ON(icplb_nr_bounds > ARRAY_SIZE(icplb_bounds)); } |