Training courses

Kernel and Embedded Linux

Bootlin training courses

Embedded Linux, kernel,
Yocto Project, Buildroot, real-time,
graphics, boot time, debugging...

Bootlin logo

Elixir Cross Referencer

  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
/***********************license start***************
 * Author: Cavium Networks
 *
 * Contact: support@caviumnetworks.com
 * This file is part of the OCTEON SDK
 *
 * Copyright (c) 2003-2012 Cavium Networks
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 *
 * This file is distributed in the hope that it will be useful, but
 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 * NONINFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this file; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 * or visit http://www.gnu.org/licenses/.
 *
 * This file may also be available under a different license from Cavium.
 * Contact Cavium Networks for more information
 ***********************license end**************************************/

#ifndef __CVMX_PEMX_DEFS_H__
#define __CVMX_PEMX_DEFS_H__

#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)

union cvmx_pemx_bar1_indexx {
	uint64_t u64;
	struct cvmx_pemx_bar1_indexx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_20_63:44;
		uint64_t addr_idx:16;
		uint64_t ca:1;
		uint64_t end_swp:2;
		uint64_t addr_v:1;
#else
		uint64_t addr_v:1;
		uint64_t end_swp:2;
		uint64_t ca:1;
		uint64_t addr_idx:16;
		uint64_t reserved_20_63:44;
#endif
	} s;
	struct cvmx_pemx_bar1_indexx_s cn61xx;
	struct cvmx_pemx_bar1_indexx_s cn63xx;
	struct cvmx_pemx_bar1_indexx_s cn63xxp1;
	struct cvmx_pemx_bar1_indexx_s cn66xx;
	struct cvmx_pemx_bar1_indexx_s cn68xx;
	struct cvmx_pemx_bar1_indexx_s cn68xxp1;
	struct cvmx_pemx_bar1_indexx_s cnf71xx;
};

union cvmx_pemx_bar2_mask {
	uint64_t u64;
	struct cvmx_pemx_bar2_mask_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_38_63:26;
		uint64_t mask:35;
		uint64_t reserved_0_2:3;
#else
		uint64_t reserved_0_2:3;
		uint64_t mask:35;
		uint64_t reserved_38_63:26;
#endif
	} s;
	struct cvmx_pemx_bar2_mask_s cn61xx;
	struct cvmx_pemx_bar2_mask_s cn66xx;
	struct cvmx_pemx_bar2_mask_s cn68xx;
	struct cvmx_pemx_bar2_mask_s cn68xxp1;
	struct cvmx_pemx_bar2_mask_s cnf71xx;
};

union cvmx_pemx_bar_ctl {
	uint64_t u64;
	struct cvmx_pemx_bar_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_7_63:57;
		uint64_t bar1_siz:3;
		uint64_t bar2_enb:1;
		uint64_t bar2_esx:2;
		uint64_t bar2_cax:1;
#else
		uint64_t bar2_cax:1;
		uint64_t bar2_esx:2;
		uint64_t bar2_enb:1;
		uint64_t bar1_siz:3;
		uint64_t reserved_7_63:57;
#endif
	} s;
	struct cvmx_pemx_bar_ctl_s cn61xx;
	struct cvmx_pemx_bar_ctl_s cn63xx;
	struct cvmx_pemx_bar_ctl_s cn63xxp1;
	struct cvmx_pemx_bar_ctl_s cn66xx;
	struct cvmx_pemx_bar_ctl_s cn68xx;
	struct cvmx_pemx_bar_ctl_s cn68xxp1;
	struct cvmx_pemx_bar_ctl_s cnf71xx;
};

union cvmx_pemx_bist_status {
	uint64_t u64;
	struct cvmx_pemx_bist_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_8_63:56;
		uint64_t retry:1;
		uint64_t rqdata0:1;
		uint64_t rqdata1:1;
		uint64_t rqdata2:1;
		uint64_t rqdata3:1;
		uint64_t rqhdr1:1;
		uint64_t rqhdr0:1;
		uint64_t sot:1;
#else
		uint64_t sot:1;
		uint64_t rqhdr0:1;
		uint64_t rqhdr1:1;
		uint64_t rqdata3:1;
		uint64_t rqdata2:1;
		uint64_t rqdata1:1;
		uint64_t rqdata0:1;
		uint64_t retry:1;
		uint64_t reserved_8_63:56;
#endif
	} s;
	struct cvmx_pemx_bist_status_s cn61xx;
	struct cvmx_pemx_bist_status_s cn63xx;
	struct cvmx_pemx_bist_status_s cn63xxp1;
	struct cvmx_pemx_bist_status_s cn66xx;
	struct cvmx_pemx_bist_status_s cn68xx;
	struct cvmx_pemx_bist_status_s cn68xxp1;
	struct cvmx_pemx_bist_status_s cnf71xx;
};

union cvmx_pemx_bist_status2 {
	uint64_t u64;
	struct cvmx_pemx_bist_status2_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_10_63:54;
		uint64_t e2p_cpl:1;
		uint64_t e2p_n:1;
		uint64_t e2p_p:1;
		uint64_t peai_p2e:1;
		uint64_t pef_tpf1:1;
		uint64_t pef_tpf0:1;
		uint64_t pef_tnf:1;
		uint64_t pef_tcf1:1;
		uint64_t pef_tc0:1;
		uint64_t ppf:1;
#else
		uint64_t ppf:1;
		uint64_t pef_tc0:1;
		uint64_t pef_tcf1:1;
		uint64_t pef_tnf:1;
		uint64_t pef_tpf0:1;
		uint64_t pef_tpf1:1;
		uint64_t peai_p2e:1;
		uint64_t e2p_p:1;
		uint64_t e2p_n:1;
		uint64_t e2p_cpl:1;
		uint64_t reserved_10_63:54;
#endif
	} s;
	struct cvmx_pemx_bist_status2_s cn61xx;
	struct cvmx_pemx_bist_status2_s cn63xx;
	struct cvmx_pemx_bist_status2_s cn63xxp1;
	struct cvmx_pemx_bist_status2_s cn66xx;
	struct cvmx_pemx_bist_status2_s cn68xx;
	struct cvmx_pemx_bist_status2_s cn68xxp1;
	struct cvmx_pemx_bist_status2_s cnf71xx;
};

union cvmx_pemx_cfg_rd {
	uint64_t u64;
	struct cvmx_pemx_cfg_rd_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t data:32;
		uint64_t addr:32;
#else
		uint64_t addr:32;
		uint64_t data:32;
#endif
	} s;
	struct cvmx_pemx_cfg_rd_s cn61xx;
	struct cvmx_pemx_cfg_rd_s cn63xx;
	struct cvmx_pemx_cfg_rd_s cn63xxp1;
	struct cvmx_pemx_cfg_rd_s cn66xx;
	struct cvmx_pemx_cfg_rd_s cn68xx;
	struct cvmx_pemx_cfg_rd_s cn68xxp1;
	struct cvmx_pemx_cfg_rd_s cnf71xx;
};

union cvmx_pemx_cfg_wr {
	uint64_t u64;
	struct cvmx_pemx_cfg_wr_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t data:32;
		uint64_t addr:32;
#else
		uint64_t addr:32;
		uint64_t data:32;
#endif
	} s;
	struct cvmx_pemx_cfg_wr_s cn61xx;
	struct cvmx_pemx_cfg_wr_s cn63xx;
	struct cvmx_pemx_cfg_wr_s cn63xxp1;
	struct cvmx_pemx_cfg_wr_s cn66xx;
	struct cvmx_pemx_cfg_wr_s cn68xx;
	struct cvmx_pemx_cfg_wr_s cn68xxp1;
	struct cvmx_pemx_cfg_wr_s cnf71xx;
};

union cvmx_pemx_cpl_lut_valid {
	uint64_t u64;
	struct cvmx_pemx_cpl_lut_valid_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_32_63:32;
		uint64_t tag:32;
#else
		uint64_t tag:32;
		uint64_t reserved_32_63:32;
#endif
	} s;
	struct cvmx_pemx_cpl_lut_valid_s cn61xx;
	struct cvmx_pemx_cpl_lut_valid_s cn63xx;
	struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
	struct cvmx_pemx_cpl_lut_valid_s cn66xx;
	struct cvmx_pemx_cpl_lut_valid_s cn68xx;
	struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
	struct cvmx_pemx_cpl_lut_valid_s cnf71xx;
};

union cvmx_pemx_ctl_status {
	uint64_t u64;
	struct cvmx_pemx_ctl_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_48_63:16;
		uint64_t auto_sd:1;
		uint64_t dnum:5;
		uint64_t pbus:8;
		uint64_t reserved_32_33:2;
		uint64_t cfg_rtry:16;
		uint64_t reserved_12_15:4;
		uint64_t pm_xtoff:1;
		uint64_t pm_xpme:1;
		uint64_t ob_p_cmd:1;
		uint64_t reserved_7_8:2;
		uint64_t nf_ecrc:1;
		uint64_t dly_one:1;
		uint64_t lnk_enb:1;
		uint64_t ro_ctlp:1;
		uint64_t fast_lm:1;
		uint64_t inv_ecrc:1;
		uint64_t inv_lcrc:1;
#else
		uint64_t inv_lcrc:1;
		uint64_t inv_ecrc:1;
		uint64_t fast_lm:1;
		uint64_t ro_ctlp:1;
		uint64_t lnk_enb:1;
		uint64_t dly_one:1;
		uint64_t nf_ecrc:1;
		uint64_t reserved_7_8:2;
		uint64_t ob_p_cmd:1;
		uint64_t pm_xpme:1;
		uint64_t pm_xtoff:1;
		uint64_t reserved_12_15:4;
		uint64_t cfg_rtry:16;
		uint64_t reserved_32_33:2;
		uint64_t pbus:8;
		uint64_t dnum:5;
		uint64_t auto_sd:1;
		uint64_t reserved_48_63:16;
#endif
	} s;
	struct cvmx_pemx_ctl_status_s cn61xx;
	struct cvmx_pemx_ctl_status_s cn63xx;
	struct cvmx_pemx_ctl_status_s cn63xxp1;
	struct cvmx_pemx_ctl_status_s cn66xx;
	struct cvmx_pemx_ctl_status_s cn68xx;
	struct cvmx_pemx_ctl_status_s cn68xxp1;
	struct cvmx_pemx_ctl_status_s cnf71xx;
};

union cvmx_pemx_dbg_info {
	uint64_t u64;
	struct cvmx_pemx_dbg_info_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_31_63:33;
		uint64_t ecrc_e:1;
		uint64_t rawwpp:1;
		uint64_t racpp:1;
		uint64_t ramtlp:1;
		uint64_t rarwdns:1;
		uint64_t caar:1;
		uint64_t racca:1;
		uint64_t racur:1;
		uint64_t rauc:1;
		uint64_t rqo:1;
		uint64_t fcuv:1;
		uint64_t rpe:1;
		uint64_t fcpvwt:1;
		uint64_t dpeoosd:1;
		uint64_t rtwdle:1;
		uint64_t rdwdle:1;
		uint64_t mre:1;
		uint64_t rte:1;
		uint64_t acto:1;
		uint64_t rvdm:1;
		uint64_t rumep:1;
		uint64_t rptamrc:1;
		uint64_t rpmerc:1;
		uint64_t rfemrc:1;
		uint64_t rnfemrc:1;
		uint64_t rcemrc:1;
		uint64_t rpoison:1;
		uint64_t recrce:1;
		uint64_t rtlplle:1;
		uint64_t rtlpmal:1;
		uint64_t spoison:1;
#else
		uint64_t spoison:1;
		uint64_t rtlpmal:1;
		uint64_t rtlplle:1;
		uint64_t recrce:1;
		uint64_t rpoison:1;
		uint64_t rcemrc:1;
		uint64_t rnfemrc:1;
		uint64_t rfemrc:1;
		uint64_t rpmerc:1;
		uint64_t rptamrc:1;
		uint64_t rumep:1;
		uint64_t rvdm:1;
		uint64_t acto:1;
		uint64_t rte:1;
		uint64_t mre:1;
		uint64_t rdwdle:1;
		uint64_t rtwdle:1;
		uint64_t dpeoosd:1;
		uint64_t fcpvwt:1;
		uint64_t rpe:1;
		uint64_t fcuv:1;
		uint64_t rqo:1;
		uint64_t rauc:1;
		uint64_t racur:1;
		uint64_t racca:1;
		uint64_t caar:1;
		uint64_t rarwdns:1;
		uint64_t ramtlp:1;
		uint64_t racpp:1;
		uint64_t rawwpp:1;
		uint64_t ecrc_e:1;
		uint64_t reserved_31_63:33;
#endif
	} s;
	struct cvmx_pemx_dbg_info_s cn61xx;
	struct cvmx_pemx_dbg_info_s cn63xx;
	struct cvmx_pemx_dbg_info_s cn63xxp1;
	struct cvmx_pemx_dbg_info_s cn66xx;
	struct cvmx_pemx_dbg_info_s cn68xx;
	struct cvmx_pemx_dbg_info_s cn68xxp1;
	struct cvmx_pemx_dbg_info_s cnf71xx;
};

union cvmx_pemx_dbg_info_en {
	uint64_t u64;
	struct cvmx_pemx_dbg_info_en_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_31_63:33;
		uint64_t ecrc_e:1;
		uint64_t rawwpp:1;
		uint64_t racpp:1;
		uint64_t ramtlp:1;
		uint64_t rarwdns:1;
		uint64_t caar:1;
		uint64_t racca:1;
		uint64_t racur:1;
		uint64_t rauc:1;
		uint64_t rqo:1;
		uint64_t fcuv:1;
		uint64_t rpe:1;
		uint64_t fcpvwt:1;
		uint64_t dpeoosd:1;
		uint64_t rtwdle:1;
		uint64_t rdwdle:1;
		uint64_t mre:1;
		uint64_t rte:1;
		uint64_t acto:1;
		uint64_t rvdm:1;
		uint64_t rumep:1;
		uint64_t rptamrc:1;
		uint64_t rpmerc:1;
		uint64_t rfemrc:1;
		uint64_t rnfemrc:1;
		uint64_t rcemrc:1;
		uint64_t rpoison:1;
		uint64_t recrce:1;
		uint64_t rtlplle:1;
		uint64_t rtlpmal:1;
		uint64_t spoison:1;
#else
		uint64_t spoison:1;
		uint64_t rtlpmal:1;
		uint64_t rtlplle:1;
		uint64_t recrce:1;
		uint64_t rpoison:1;
		uint64_t rcemrc:1;
		uint64_t rnfemrc:1;
		uint64_t rfemrc:1;
		uint64_t rpmerc:1;
		uint64_t rptamrc:1;
		uint64_t rumep:1;
		uint64_t rvdm:1;
		uint64_t acto:1;
		uint64_t rte:1;
		uint64_t mre:1;
		uint64_t rdwdle:1;
		uint64_t rtwdle:1;
		uint64_t dpeoosd:1;
		uint64_t fcpvwt:1;
		uint64_t rpe:1;
		uint64_t fcuv:1;
		uint64_t rqo:1;
		uint64_t rauc:1;
		uint64_t racur:1;
		uint64_t racca:1;
		uint64_t caar:1;
		uint64_t rarwdns:1;
		uint64_t ramtlp:1;
		uint64_t racpp:1;
		uint64_t rawwpp:1;
		uint64_t ecrc_e:1;
		uint64_t reserved_31_63:33;
#endif
	} s;
	struct cvmx_pemx_dbg_info_en_s cn61xx;
	struct cvmx_pemx_dbg_info_en_s cn63xx;
	struct cvmx_pemx_dbg_info_en_s cn63xxp1;
	struct cvmx_pemx_dbg_info_en_s cn66xx;
	struct cvmx_pemx_dbg_info_en_s cn68xx;
	struct cvmx_pemx_dbg_info_en_s cn68xxp1;
	struct cvmx_pemx_dbg_info_en_s cnf71xx;
};

union cvmx_pemx_diag_status {
	uint64_t u64;
	struct cvmx_pemx_diag_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_4_63:60;
		uint64_t pm_dst:1;
		uint64_t pm_stat:1;
		uint64_t pm_en:1;
		uint64_t aux_en:1;
#else
		uint64_t aux_en:1;
		uint64_t pm_en:1;
		uint64_t pm_stat:1;
		uint64_t pm_dst:1;
		uint64_t reserved_4_63:60;
#endif
	} s;
	struct cvmx_pemx_diag_status_s cn61xx;
	struct cvmx_pemx_diag_status_s cn63xx;
	struct cvmx_pemx_diag_status_s cn63xxp1;
	struct cvmx_pemx_diag_status_s cn66xx;
	struct cvmx_pemx_diag_status_s cn68xx;
	struct cvmx_pemx_diag_status_s cn68xxp1;
	struct cvmx_pemx_diag_status_s cnf71xx;
};

union cvmx_pemx_inb_read_credits {
	uint64_t u64;
	struct cvmx_pemx_inb_read_credits_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_6_63:58;
		uint64_t num:6;
#else
		uint64_t num:6;
		uint64_t reserved_6_63:58;
#endif
	} s;
	struct cvmx_pemx_inb_read_credits_s cn61xx;
	struct cvmx_pemx_inb_read_credits_s cn66xx;
	struct cvmx_pemx_inb_read_credits_s cn68xx;
	struct cvmx_pemx_inb_read_credits_s cnf71xx;
};

union cvmx_pemx_int_enb {
	uint64_t u64;
	struct cvmx_pemx_int_enb_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_14_63:50;
		uint64_t crs_dr:1;
		uint64_t crs_er:1;
		uint64_t rdlk:1;
		uint64_t exc:1;
		uint64_t un_bx:1;
		uint64_t un_b2:1;
		uint64_t un_b1:1;
		uint64_t up_bx:1;
		uint64_t up_b2:1;
		uint64_t up_b1:1;
		uint64_t pmem:1;
		uint64_t pmei:1;
		uint64_t se:1;
		uint64_t aeri:1;
#else
		uint64_t aeri:1;
		uint64_t se:1;
		uint64_t pmei:1;
		uint64_t pmem:1;
		uint64_t up_b1:1;
		uint64_t up_b2:1;
		uint64_t up_bx:1;
		uint64_t un_b1:1;
		uint64_t un_b2:1;
		uint64_t un_bx:1;
		uint64_t exc:1;
		uint64_t rdlk:1;
		uint64_t crs_er:1;
		uint64_t crs_dr:1;
		uint64_t reserved_14_63:50;
#endif
	} s;
	struct cvmx_pemx_int_enb_s cn61xx;
	struct cvmx_pemx_int_enb_s cn63xx;
	struct cvmx_pemx_int_enb_s cn63xxp1;
	struct cvmx_pemx_int_enb_s cn66xx;
	struct cvmx_pemx_int_enb_s cn68xx;
	struct cvmx_pemx_int_enb_s cn68xxp1;
	struct cvmx_pemx_int_enb_s cnf71xx;
};

union cvmx_pemx_int_enb_int {
	uint64_t u64;
	struct cvmx_pemx_int_enb_int_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_14_63:50;
		uint64_t crs_dr:1;
		uint64_t crs_er:1;
		uint64_t rdlk:1;
		uint64_t exc:1;
		uint64_t un_bx:1;
		uint64_t un_b2:1;
		uint64_t un_b1:1;
		uint64_t up_bx:1;
		uint64_t up_b2:1;
		uint64_t up_b1:1;
		uint64_t pmem:1;
		uint64_t pmei:1;
		uint64_t se:1;
		uint64_t aeri:1;
#else
		uint64_t aeri:1;
		uint64_t se:1;
		uint64_t pmei:1;
		uint64_t pmem:1;
		uint64_t up_b1:1;
		uint64_t up_b2:1;
		uint64_t up_bx:1;
		uint64_t un_b1:1;
		uint64_t un_b2:1;
		uint64_t un_bx:1;
		uint64_t exc:1;
		uint64_t rdlk:1;
		uint64_t crs_er:1;
		uint64_t crs_dr:1;
		uint64_t reserved_14_63:50;
#endif
	} s;
	struct cvmx_pemx_int_enb_int_s cn61xx;
	struct cvmx_pemx_int_enb_int_s cn63xx;
	struct cvmx_pemx_int_enb_int_s cn63xxp1;
	struct cvmx_pemx_int_enb_int_s cn66xx;
	struct cvmx_pemx_int_enb_int_s cn68xx;
	struct cvmx_pemx_int_enb_int_s cn68xxp1;
	struct cvmx_pemx_int_enb_int_s cnf71xx;
};

union cvmx_pemx_int_sum {
	uint64_t u64;
	struct cvmx_pemx_int_sum_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_14_63:50;
		uint64_t crs_dr:1;
		uint64_t crs_er:1;
		uint64_t rdlk:1;
		uint64_t exc:1;
		uint64_t un_bx:1;
		uint64_t un_b2:1;
		uint64_t un_b1:1;
		uint64_t up_bx:1;
		uint64_t up_b2:1;
		uint64_t up_b1:1;
		uint64_t pmem:1;
		uint64_t pmei:1;
		uint64_t se:1;
		uint64_t aeri:1;
#else
		uint64_t aeri:1;
		uint64_t se:1;
		uint64_t pmei:1;
		uint64_t pmem:1;
		uint64_t up_b1:1;
		uint64_t up_b2:1;
		uint64_t up_bx:1;
		uint64_t un_b1:1;
		uint64_t un_b2:1;
		uint64_t un_bx:1;
		uint64_t exc:1;
		uint64_t rdlk:1;
		uint64_t crs_er:1;
		uint64_t crs_dr:1;
		uint64_t reserved_14_63:50;
#endif
	} s;
	struct cvmx_pemx_int_sum_s cn61xx;
	struct cvmx_pemx_int_sum_s cn63xx;
	struct cvmx_pemx_int_sum_s cn63xxp1;
	struct cvmx_pemx_int_sum_s cn66xx;
	struct cvmx_pemx_int_sum_s cn68xx;
	struct cvmx_pemx_int_sum_s cn68xxp1;
	struct cvmx_pemx_int_sum_s cnf71xx;
};

union cvmx_pemx_p2n_bar0_start {
	uint64_t u64;
	struct cvmx_pemx_p2n_bar0_start_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t addr:50;
		uint64_t reserved_0_13:14;
#else
		uint64_t reserved_0_13:14;
		uint64_t addr:50;
#endif
	} s;
	struct cvmx_pemx_p2n_bar0_start_s cn61xx;
	struct cvmx_pemx_p2n_bar0_start_s cn63xx;
	struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
	struct cvmx_pemx_p2n_bar0_start_s cn66xx;
	struct cvmx_pemx_p2n_bar0_start_s cn68xx;
	struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
	struct cvmx_pemx_p2n_bar0_start_s cnf71xx;
};

union cvmx_pemx_p2n_bar1_start {
	uint64_t u64;
	struct cvmx_pemx_p2n_bar1_start_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t addr:38;
		uint64_t reserved_0_25:26;
#else
		uint64_t reserved_0_25:26;
		uint64_t addr:38;
#endif
	} s;
	struct cvmx_pemx_p2n_bar1_start_s cn61xx;
	struct cvmx_pemx_p2n_bar1_start_s cn63xx;
	struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
	struct cvmx_pemx_p2n_bar1_start_s cn66xx;
	struct cvmx_pemx_p2n_bar1_start_s cn68xx;
	struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
	struct cvmx_pemx_p2n_bar1_start_s cnf71xx;
};

union cvmx_pemx_p2n_bar2_start {
	uint64_t u64;
	struct cvmx_pemx_p2n_bar2_start_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t addr:23;
		uint64_t reserved_0_40:41;
#else
		uint64_t reserved_0_40:41;
		uint64_t addr:23;
#endif
	} s;
	struct cvmx_pemx_p2n_bar2_start_s cn61xx;
	struct cvmx_pemx_p2n_bar2_start_s cn63xx;
	struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
	struct cvmx_pemx_p2n_bar2_start_s cn66xx;
	struct cvmx_pemx_p2n_bar2_start_s cn68xx;
	struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
	struct cvmx_pemx_p2n_bar2_start_s cnf71xx;
};

union cvmx_pemx_p2p_barx_end {
	uint64_t u64;
	struct cvmx_pemx_p2p_barx_end_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t addr:52;
		uint64_t reserved_0_11:12;
#else
		uint64_t reserved_0_11:12;
		uint64_t addr:52;
#endif
	} s;
	struct cvmx_pemx_p2p_barx_end_s cn63xx;
	struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
	struct cvmx_pemx_p2p_barx_end_s cn66xx;
	struct cvmx_pemx_p2p_barx_end_s cn68xx;
	struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
};

union cvmx_pemx_p2p_barx_start {
	uint64_t u64;
	struct cvmx_pemx_p2p_barx_start_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t addr:52;
		uint64_t reserved_0_11:12;
#else
		uint64_t reserved_0_11:12;
		uint64_t addr:52;
#endif
	} s;
	struct cvmx_pemx_p2p_barx_start_s cn63xx;
	struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
	struct cvmx_pemx_p2p_barx_start_s cn66xx;
	struct cvmx_pemx_p2p_barx_start_s cn68xx;
	struct cvmx_pemx_p2p_barx_start_s cn68xxp1;
};

union cvmx_pemx_tlp_credits {
	uint64_t u64;
	struct cvmx_pemx_tlp_credits_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_56_63:8;
		uint64_t peai_ppf:8;
		uint64_t pem_cpl:8;
		uint64_t pem_np:8;
		uint64_t pem_p:8;
		uint64_t sli_cpl:8;
		uint64_t sli_np:8;
		uint64_t sli_p:8;
#else
		uint64_t sli_p:8;
		uint64_t sli_np:8;
		uint64_t sli_cpl:8;
		uint64_t pem_p:8;
		uint64_t pem_np:8;
		uint64_t pem_cpl:8;
		uint64_t peai_ppf:8;
		uint64_t reserved_56_63:8;
#endif
	} s;
	struct cvmx_pemx_tlp_credits_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_56_63:8;
		uint64_t peai_ppf:8;
		uint64_t reserved_24_47:24;
		uint64_t sli_cpl:8;
		uint64_t sli_np:8;
		uint64_t sli_p:8;
#else
		uint64_t sli_p:8;
		uint64_t sli_np:8;
		uint64_t sli_cpl:8;
		uint64_t reserved_24_47:24;
		uint64_t peai_ppf:8;
		uint64_t reserved_56_63:8;
#endif
	} cn61xx;
	struct cvmx_pemx_tlp_credits_s cn63xx;
	struct cvmx_pemx_tlp_credits_s cn63xxp1;
	struct cvmx_pemx_tlp_credits_s cn66xx;
	struct cvmx_pemx_tlp_credits_s cn68xx;
	struct cvmx_pemx_tlp_credits_s cn68xxp1;
	struct cvmx_pemx_tlp_credits_cn61xx cnf71xx;
};

#endif