[ { "BriefDescription": "ddr bandwidth read (CPU traffic only) (MB/sec). ", "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", "ScaleUnit": "6.4e-05MiB", "UMask": "0x01", "Unit": "imc" }, { "BriefDescription": "ddr bandwidth write (CPU traffic only) (MB/sec). ", "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", "ScaleUnit": "6.4e-05MiB", "UMask": "0x02", "Unit": "imc" }, { "BriefDescription": "mcdram bandwidth read (CPU traffic only) (MB/sec). ", "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_E_RPQ_INSERTS", "PerPkg": "1", "ScaleUnit": "6.4e-05MiB", "UMask": "0x01", "Unit": "edc_eclk" }, { "BriefDescription": "mcdram bandwidth write (CPU traffic only) (MB/sec). ", "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_E_WPQ_INSERTS", "PerPkg": "1", "ScaleUnit": "6.4e-05MiB", "UMask": "0x01", "Unit": "edc_eclk" } ] |