# SPDX-License-Identifier: GPL-2.0
config [31mCONFIG_ARM[0m
bool
default y
select [31mCONFIG_ARCH_32BIT_OFF_T[0m
select [31mCONFIG_ARCH_CLOCKSOURCE_DATA[0m
select [31mCONFIG_ARCH_HAS_BINFMT_FLAT[0m
select [31mCONFIG_ARCH_HAS_DEBUG_VIRTUAL[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED[0m
select [31mCONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN[0m if [31mCONFIG_SWIOTLB[0m
select [31mCONFIG_ARCH_HAS_DMA_WRITE_COMBINE[0m if ![31mCONFIG_ARM_DMA_MEM_BUFFERABLE[0m
select [31mCONFIG_ARCH_HAS_ELF_RANDOMIZE[0m
select [31mCONFIG_ARCH_HAS_FORTIFY_SOURCE[0m
select [31mCONFIG_ARCH_HAS_KEEPINITRD[0m
select [31mCONFIG_ARCH_HAS_KCOV[0m
select [31mCONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE[0m
select [31mCONFIG_ARCH_HAS_PTE_SPECIAL[0m if [31mCONFIG_ARM_LPAE[0m
select [31mCONFIG_ARCH_HAS_PHYS_TO_DMA[0m
select [31mCONFIG_ARCH_HAS_SETUP_DMA_OPS[0m
select [31mCONFIG_ARCH_HAS_SET_MEMORY[0m
select [31mCONFIG_ARCH_HAS_STRICT_KERNEL_RWX[0m if [31mCONFIG_MMU[0m && ![31mCONFIG_XIP_KERNEL[0m
select [31mCONFIG_ARCH_HAS_STRICT_MODULE_RWX[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE[0m if [31mCONFIG_SWIOTLB[0m
select [31mCONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU[0m if [31mCONFIG_SWIOTLB[0m
select [31mCONFIG_ARCH_HAS_TEARDOWN_DMA_OPS[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_ARCH_HAS_TICK_BROADCAST[0m if [31mCONFIG_GENERIC_CLOCKEVENTS_BROADCAST[0m
select [31mCONFIG_ARCH_HAVE_CUSTOM_GPIO_H[0m
select [31mCONFIG_ARCH_HAS_GCOV_PROFILE_ALL[0m
select [31mCONFIG_ARCH_KEEP_MEMBLOCK[0m if [31mCONFIG_HAVE_ARCH_PFN_VALID[0m || [31mCONFIG_KEXEC[0m
select [31mCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT[0m
select [31mCONFIG_ARCH_NO_SG_CHAIN[0m if ![31mCONFIG_ARM_HAS_SG_CHAIN[0m
select [31mCONFIG_ARCH_OPTIONAL_KERNEL_RWX[0m if [31mCONFIG_ARCH_HAS_STRICT_KERNEL_RWX[0m
select [31mCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT[0m if [31mCONFIG_CPU_V7[0m
select [31mCONFIG_ARCH_SUPPORTS_ATOMIC_RMW[0m
select [31mCONFIG_ARCH_USE_BUILTIN_BSWAP[0m
select [31mCONFIG_ARCH_USE_CMPXCHG_LOCKREF[0m
select [31mCONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_ARCH_WANT_IPC_PARSE_VERSION[0m
select [31mCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK[0m
select [31mCONFIG_BUILDTIME_EXTABLE_SORT[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CLONE_BACKWARDS[0m
select [31mCONFIG_CPU_PM[0m if [31mCONFIG_SUSPEND[0m || [31mCONFIG_CPU_IDLE[0m
select [31mCONFIG_DCACHE_WORD_ACCESS[0m if [31mCONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS[0m
select [31mCONFIG_DMA_DECLARE_COHERENT[0m
select [31mCONFIG_DMA_REMAP[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_EDAC_SUPPORT[0m
select [31mCONFIG_EDAC_ATOMIC_SCRUB[0m
select [31mCONFIG_GENERIC_ALLOCATOR[0m
select [31mCONFIG_GENERIC_ARCH_TOPOLOGY[0m if [31mCONFIG_ARM_CPU_TOPOLOGY[0m
select [31mCONFIG_GENERIC_ATOMIC64[0m if [31mCONFIG_CPU_V7M[0m || [31mCONFIG_CPU_V6[0m || ![31mCONFIG_CPU_32v6K[0m || ![31mCONFIG_AEABI[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS_BROADCAST[0m if [31mCONFIG_SMP[0m
select [31mCONFIG_GENERIC_CPU_AUTOPROBE[0m
select [31mCONFIG_GENERIC_EARLY_IOREMAP[0m
select [31mCONFIG_GENERIC_IDLE_POLL_SETUP[0m
select [31mCONFIG_GENERIC_IRQ_PROBE[0m
select [31mCONFIG_GENERIC_IRQ_SHOW[0m
select [31mCONFIG_GENERIC_IRQ_SHOW_LEVEL[0m
select [31mCONFIG_GENERIC_PCI_IOMAP[0m
select [31mCONFIG_GENERIC_SCHED_CLOCK[0m
select [31mCONFIG_GENERIC_SMP_IDLE_THREAD[0m
select [31mCONFIG_GENERIC_STRNCPY_FROM_USER[0m
select [31mCONFIG_GENERIC_STRNLEN_USER[0m
select [31mCONFIG_HANDLE_DOMAIN_IRQ[0m
select [31mCONFIG_HARDIRQS_SW_RESEND[0m
select [31mCONFIG_HAVE_ARCH_AUDITSYSCALL[0m if [31mCONFIG_AEABI[0m && ![31mCONFIG_OABI_COMPAT[0m
select [31mCONFIG_HAVE_ARCH_BITREVERSE[0m if ([31mCONFIG_CPU_32v7M[0m || [31mCONFIG_CPU_32v7[0m) && ![31mCONFIG_CPU_32v6[0m
select [31mCONFIG_HAVE_ARCH_JUMP_LABEL[0m if ![31mCONFIG_XIP_KERNEL[0m && ![31mCONFIG_CPU_ENDIAN_BE32[0m && [31mCONFIG_MMU[0m
select [31mCONFIG_HAVE_ARCH_KGDB[0m if ![31mCONFIG_CPU_ENDIAN_BE32[0m && [31mCONFIG_MMU[0m
select [31mCONFIG_HAVE_ARCH_MMAP_RND_BITS[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_HAVE_ARCH_SECCOMP_FILTER[0m if [31mCONFIG_AEABI[0m && ![31mCONFIG_OABI_COMPAT[0m
select [31mCONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST[0m
select [31mCONFIG_HAVE_ARCH_TRACEHOOK[0m
select [31mCONFIG_HAVE_ARM_SMCCC[0m if [31mCONFIG_CPU_V7[0m
select [31mCONFIG_HAVE_EBPF_JIT[0m if ![31mCONFIG_CPU_ENDIAN_BE32[0m
select [31mCONFIG_HAVE_CONTEXT_TRACKING[0m
select [31mCONFIG_HAVE_C_RECORDMCOUNT[0m
select [31mCONFIG_HAVE_DEBUG_KMEMLEAK[0m
select [31mCONFIG_HAVE_DMA_CONTIGUOUS[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_HAVE_DYNAMIC_FTRACE[0m if ![31mCONFIG_XIP_KERNEL[0m && ![31mCONFIG_CPU_ENDIAN_BE32[0m && [31mCONFIG_MMU[0m
select [31mCONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS[0m if [31mCONFIG_HAVE_DYNAMIC_FTRACE[0m
select [31mCONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS[0m if ([31mCONFIG_CPU_V6[0m || [31mCONFIG_CPU_V6K[0m || [31mCONFIG_CPU_V7[0m) && [31mCONFIG_MMU[0m
select [31mCONFIG_HAVE_EXIT_THREAD[0m
select [31mCONFIG_HAVE_FAST_GUP[0m if [31mCONFIG_ARM_LPAE[0m
select [31mCONFIG_HAVE_FTRACE_MCOUNT_RECORD[0m if ![31mCONFIG_XIP_KERNEL[0m
select [31mCONFIG_HAVE_FUNCTION_GRAPH_TRACER[0m if ![31mCONFIG_THUMB2_KERNEL[0m && ![31mCONFIG_CC_IS_CLANG[0m
select [31mCONFIG_HAVE_FUNCTION_TRACER[0m if ![31mCONFIG_XIP_KERNEL[0m && ([31mCONFIG_CC_IS_GCC[0m || [31mCONFIG_CLANG_VERSION[0m >= 100000)
select [31mCONFIG_HAVE_GCC_PLUGINS[0m
select [31mCONFIG_HAVE_HW_BREAKPOINT[0m if [31mCONFIG_PERF_EVENTS[0m && ([31mCONFIG_CPU_V6[0m || [31mCONFIG_CPU_V6K[0m || [31mCONFIG_CPU_V7[0m)
select [31mCONFIG_HAVE_IDE[0m if [31mCONFIG_PCI[0m || [31mCONFIG_ISA[0m || [31mCONFIG_PCMCIA[0m
select [31mCONFIG_HAVE_IRQ_TIME_ACCOUNTING[0m
select [31mCONFIG_HAVE_KERNEL_GZIP[0m
select [31mCONFIG_HAVE_KERNEL_LZ4[0m
select [31mCONFIG_HAVE_KERNEL_LZMA[0m
select [31mCONFIG_HAVE_KERNEL_LZO[0m
select [31mCONFIG_HAVE_KERNEL_XZ[0m
select [31mCONFIG_HAVE_KPROBES[0m if ![31mCONFIG_XIP_KERNEL[0m && ![31mCONFIG_CPU_ENDIAN_BE32[0m && ![31mCONFIG_CPU_V7M[0m
select [31mCONFIG_HAVE_KRETPROBES[0m if [31mCONFIG_HAVE_KPROBES[0m
select [31mCONFIG_HAVE_MOD_ARCH_SPECIFIC[0m
select [31mCONFIG_HAVE_NMI[0m
select [31mCONFIG_HAVE_OPROFILE[0m if [31mCONFIG_HAVE_PERF_EVENTS[0m
select [31mCONFIG_HAVE_OPTPROBES[0m if ![31mCONFIG_THUMB2_KERNEL[0m
select [31mCONFIG_HAVE_PERF_EVENTS[0m
select [31mCONFIG_HAVE_PERF_REGS[0m
select [31mCONFIG_HAVE_PERF_USER_STACK_DUMP[0m
select [31mCONFIG_HAVE_RCU_TABLE_FREE[0m if [31mCONFIG_SMP[0m && [31mCONFIG_ARM_LPAE[0m
select [31mCONFIG_HAVE_REGS_AND_STACK_ACCESS_API[0m
select [31mCONFIG_HAVE_RSEQ[0m
select [31mCONFIG_HAVE_STACKPROTECTOR[0m
select [31mCONFIG_HAVE_SYSCALL_TRACEPOINTS[0m
select [31mCONFIG_HAVE_UID16[0m
select [31mCONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN[0m
select [31mCONFIG_IRQ_FORCED_THREADING[0m
select [31mCONFIG_MODULES_USE_ELF_REL[0m
select [31mCONFIG_NEED_DMA_MAP_STATE[0m
select [31mCONFIG_OF_EARLY_FLATTREE[0m if [31mCONFIG_OF[0m
select [31mCONFIG_OLD_SIGACTION[0m
select [31mCONFIG_OLD_SIGSUSPEND3[0m
select [31mCONFIG_PCI_SYSCALL[0m if [31mCONFIG_PCI[0m
select [31mCONFIG_PERF_USE_VMALLOC[0m
select [31mCONFIG_REFCOUNT_FULL[0m
select [31mCONFIG_RTC_LIB[0m
select [31mCONFIG_SYS_SUPPORTS_APM_EMULATION[0m
# Above selects are sorted alphabetically; please add new ones
# according to that. Thanks.
help
The [31mCONFIG_ARM[0m series is a line of low-power-consumption RISC chip designs
licensed by [31mCONFIG_ARM[0m Ltd and targeted at embedded applications and
handhelds such as the Compaq IPAQ. [31mCONFIG_ARM[0m-based PCs are no longer
manufactured, but legacy [31mCONFIG_ARM[0m-based PC hardware remains popular in
Europe. There is an [31mCONFIG_ARM[0m Linux project with a web page at
<http://www.arm.linux.org.uk/>.
config [31mCONFIG_ARM_HAS_SG_CHAIN[0m
bool
config [31mCONFIG_ARM_DMA_USE_IOMMU[0m
bool
select [31mCONFIG_ARM_HAS_SG_CHAIN[0m
select [31mCONFIG_NEED_SG_DMA_LENGTH[0m
if [31mCONFIG_ARM_DMA_USE_IOMMU[0m
config [31mCONFIG_ARM_DMA_IOMMU_ALIGNMENT[0m
int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
range 4 9
default 8
help
DMA mapping framework by default aligns all buffers to the smallest
PAGE_SIZE order which is greater than or equal to the requested buffer
size. This works well for buffers up to a few hundreds kilobytes, but
for larger buffers it just a waste of address space. Drivers which has
relatively small addressing window (like 64Mib) might run out of
virtual space with just a few allocations.
With this parameter you can specify the maximum PAGE_SIZE order for
DMA IOMMU buffers. Larger buffers will be aligned only to this
specified order. The order is expressed as a power of two multiplied
by the PAGE_SIZE.
endif
config [31mCONFIG_SYS_SUPPORTS_APM_EMULATION[0m
bool
config [31mCONFIG_HAVE_TCM[0m
bool
select [31mCONFIG_GENERIC_ALLOCATOR[0m
config [31mCONFIG_HAVE_PROC_CPU[0m
bool
config [31mCONFIG_NO_IOPORT_MAP[0m
bool
config [31mCONFIG_SBUS[0m
bool
config [31mCONFIG_STACKTRACE_SUPPORT[0m
bool
default y
config [31mCONFIG_LOCKDEP_SUPPORT[0m
bool
default y
config [31mCONFIG_TRACE_IRQFLAGS_SUPPORT[0m
bool
default ![31mCONFIG_CPU_V7M[0m
config [31mCONFIG_ARCH_HAS_ILOG2_U32[0m
bool
config [31mCONFIG_ARCH_HAS_ILOG2_U64[0m
bool
config [31mCONFIG_ARCH_HAS_BANDGAP[0m
bool
config [31mCONFIG_FIX_EARLYCON_MEM[0m
def_bool y if [31mCONFIG_MMU[0m
config [31mCONFIG_GENERIC_HWEIGHT[0m
bool
default y
config [31mCONFIG_GENERIC_CALIBRATE_DELAY[0m
bool
default y
config [31mCONFIG_ARCH_MAY_HAVE_PC_FDC[0m
bool
config [31mCONFIG_ZONE_DMA[0m
bool
config [31mCONFIG_ARCH_SUPPORTS_UPROBES[0m
def_bool y
config [31mCONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK[0m
bool
config [31mCONFIG_GENERIC_ISA_DMA[0m
bool
config [31mCONFIG_FIQ[0m
bool
config [31mCONFIG_NEED_RET_TO_USER[0m
bool
config [31mCONFIG_ARCH_MTD_XIP[0m
bool
config [31mCONFIG_ARM_PATCH_PHYS_VIRT[0m
bool "Patch physical to virtual translations at runtime" if [31mCONFIG_EMBEDDED[0m
default y
depends on ![31mCONFIG_XIP_KERNEL[0m && [31mCONFIG_MMU[0m
help
Patch phys-to-virt and virt-to-phys translation functions at
boot and module load time according to the position of the
kernel in system memory.
This can only be used with non-XIP [31mCONFIG_MMU[0m kernels where the base
of physical memory is at a 16MB boundary.
Only disable this option if you know that you do not require
this feature (eg, building a kernel for a single machine) and
you need to shrink the kernel to the minimal size.
config [31mCONFIG_NEED_MACH_IO_H[0m
bool
help
Select this when mach/io.h is required to provide special
definitions for this platform. The need for mach/io.h should
be avoided when possible.
config [31mCONFIG_NEED_MACH_MEMORY_H[0m
bool
help
Select this when mach/memory.h is required to provide special
definitions for this platform. The need for mach/memory.h should
be avoided when possible.
config [31mCONFIG_PHYS_OFFSET[0m
hex "Physical address of main memory" if [31mCONFIG_MMU[0m
depends on ![31mCONFIG_ARM_PATCH_PHYS_VIRT[0m
default [31mCONFIG_DRAM_BASE[0m if ![31mCONFIG_MMU[0m
default 0x00000000 if [31mCONFIG_ARCH_EBSA110[0m || \
[31mCONFIG_ARCH_FOOTBRIDGE[0m || \
[31mCONFIG_ARCH_INTEGRATOR[0m || \
[31mCONFIG_ARCH_REALVIEW[0m
default 0x10000000 if [31mCONFIG_ARCH_OMAP1[0m || [31mCONFIG_ARCH_RPC[0m
default 0x20000000 if [31mCONFIG_ARCH_S5PV210[0m
default 0xc0000000 if [31mCONFIG_ARCH_SA1100[0m
help
Please provide the physical address corresponding to the
location of main memory in your system.
config [31mCONFIG_GENERIC_BUG[0m
def_bool y
depends on [31mCONFIG_BUG[0m
config [31mCONFIG_PGTABLE_LEVELS[0m
int
default 3 if [31mCONFIG_ARM_LPAE[0m
default 2
menu "System Type"
config [31mCONFIG_MMU[0m
bool "MMU-based Paged Memory Management Support"
default y
help
Select if you want [31mCONFIG_MMU[0m-based virtualised addressing space
support by paged memory management. If unsure, say 'Y'.
config [31mCONFIG_ARCH_MMAP_RND_BITS_MIN[0m
default 8
config [31mCONFIG_ARCH_MMAP_RND_BITS_MAX[0m
default 14 if [31mCONFIG_PAGE_OFFSET[0m=0x40000000
default 15 if [31mCONFIG_PAGE_OFFSET[0m=0x80000000
default 16
#
# The "ARM system type" choice list is ordered alphabetically by option
# text. Please add new entries in the option alphabetic order.
#
choice
prompt "ARM system type"
default [31mCONFIG_ARM_SINGLE_ARMV7M[0m if ![31mCONFIG_MMU[0m
default [31mCONFIG_ARCH_MULTIPLATFORM[0m if [31mCONFIG_MMU[0m
config [31mCONFIG_ARCH_MULTIPLATFORM[0m
bool "Allow multiple platforms to be selected"
depends on [31mCONFIG_MMU[0m
select [31mCONFIG_ARM_HAS_SG_CHAIN[0m
select [31mCONFIG_ARM_PATCH_PHYS_VIRT[0m
select [31mCONFIG_AUTO_ZRELADDR[0m
select [31mCONFIG_TIMER_OF[0m
select [31mCONFIG_COMMON_CLK[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select [31mCONFIG_HAVE_PCI[0m
select [31mCONFIG_PCI_DOMAINS_GENERIC[0m if [31mCONFIG_PCI[0m
select [31mCONFIG_SPARSE_IRQ[0m
select [31mCONFIG_USE_OF[0m
config [31mCONFIG_ARM_SINGLE_ARMV7M[0m
bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
depends on ![31mCONFIG_MMU[0m
select [31mCONFIG_ARM_NVIC[0m
select [31mCONFIG_AUTO_ZRELADDR[0m
select [31mCONFIG_TIMER_OF[0m
select [31mCONFIG_COMMON_CLK[0m
select [31mCONFIG_CPU_V7M[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_NO_IOPORT_MAP[0m
select [31mCONFIG_SPARSE_IRQ[0m
select [31mCONFIG_USE_OF[0m
config [31mCONFIG_ARCH_EBSA110[0m
bool "EBSA-110"
select [31mCONFIG_ARCH_USES_GETTIMEOFFSET[0m
select [31mCONFIG_CPU_SA110[0m
select [31mCONFIG_ISA[0m
select [31mCONFIG_NEED_MACH_IO_H[0m
select [31mCONFIG_NEED_MACH_MEMORY_H[0m
select [31mCONFIG_NO_IOPORT_MAP[0m
help
This is an evaluation board for the StrongARM processor available
from Digital. It has limited hardware on-board, including an
Ethernet interface, two [31mCONFIG_PCMCIA[0m sockets, two serial ports and a
parallel port.
config [31mCONFIG_ARCH_EP93XX[0m
bool "EP93xx-based"
select [31mCONFIG_ARCH_SPARSEMEM_ENABLE[0m
select [31mCONFIG_ARM_AMBA[0m
imply [31mCONFIG_ARM_PATCH_PHYS_VIRT[0m
select [31mCONFIG_ARM_VIC[0m
select [31mCONFIG_AUTO_ZRELADDR[0m
select [31mCONFIG_CLKDEV_LOOKUP[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_CPU_ARM920T[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_GPIOLIB[0m
help
This enables support for the Cirrus EP93xx series of CPUs.
config [31mCONFIG_ARCH_FOOTBRIDGE[0m
bool "FootBridge"
select [31mCONFIG_CPU_SA110[0m
select [31mCONFIG_FOOTBRIDGE[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_HAVE_IDE[0m
select [31mCONFIG_NEED_MACH_IO_H[0m if ![31mCONFIG_MMU[0m
select [31mCONFIG_NEED_MACH_MEMORY_H[0m
help
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
config [31mCONFIG_ARCH_IOP32X[0m
bool "IOP32x-based"
depends on [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_XSCALE[0m
select [31mCONFIG_GPIO_IOP[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_NEED_RET_TO_USER[0m
select [31mCONFIG_FORCE_PCI[0m
select [31mCONFIG_PLAT_IOP[0m
help
Support for Intel's 80219 and IOP32X (XScale) family of
processors.
config [31mCONFIG_ARCH_IXP4XX[0m
bool "IXP4xx-based"
depends on [31mCONFIG_MMU[0m
select [31mCONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK[0m
select [31mCONFIG_ARCH_SUPPORTS_BIG_ENDIAN[0m
select [31mCONFIG_CPU_XSCALE[0m
select [31mCONFIG_DMABOUNCE[0m if [31mCONFIG_PCI[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select [31mCONFIG_GPIO_IXP4XX[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_HAVE_PCI[0m
select [31mCONFIG_IXP4XX_IRQ[0m
select [31mCONFIG_IXP4XX_TIMER[0m
select [31mCONFIG_NEED_MACH_IO_H[0m
select [31mCONFIG_USB_EHCI_BIG_ENDIAN_DESC[0m
select [31mCONFIG_USB_EHCI_BIG_ENDIAN_MMIO[0m
help
Support for Intel's IXP4XX (XScale) family of processors.
config [31mCONFIG_ARCH_DOVE[0m
bool "Marvell Dove"
select [31mCONFIG_CPU_PJ4[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_HAVE_PCI[0m
select [31mCONFIG_MVEBU_MBUS[0m
select [31mCONFIG_PINCTRL[0m
select [31mCONFIG_PINCTRL_DOVE[0m
select [31mCONFIG_PLAT_ORION_LEGACY[0m
select [31mCONFIG_SPARSE_IRQ[0m
select [31mCONFIG_PM_GENERIC_DOMAINS[0m if [31mCONFIG_PM[0m
help
Support for the Marvell Dove SoC 88AP510
config [31mCONFIG_ARCH_PXA[0m
bool "PXA2xx/PXA3xx-based"
depends on [31mCONFIG_MMU[0m
select [31mCONFIG_ARCH_MTD_XIP[0m
select [31mCONFIG_ARM_CPU_SUSPEND[0m if [31mCONFIG_PM[0m
select [31mCONFIG_AUTO_ZRELADDR[0m
select [31mCONFIG_COMMON_CLK[0m
select [31mCONFIG_CLKDEV_LOOKUP[0m
select [31mCONFIG_CLKSRC_PXA[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_TIMER_OF[0m
select [31mCONFIG_CPU_XSCALE[0m if ![31mCONFIG_CPU_XSC3[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select [31mCONFIG_GPIO_PXA[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_HAVE_IDE[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_PLAT_PXA[0m
select [31mCONFIG_SPARSE_IRQ[0m
help
Support for Intel/Marvell's PXA2xx/[31mCONFIG_PXA3xx[0m processor line.
config [31mCONFIG_ARCH_RPC[0m
bool "RiscPC"
depends on [31mCONFIG_MMU[0m
select [31mCONFIG_ARCH_ACORN[0m
select [31mCONFIG_ARCH_MAY_HAVE_PC_FDC[0m
select [31mCONFIG_ARCH_SPARSEMEM_ENABLE[0m
select [31mCONFIG_ARM_HAS_SG_CHAIN[0m
select [31mCONFIG_CPU_SA110[0m
select [31mCONFIG_FIQ[0m
select [31mCONFIG_HAVE_IDE[0m
select [31mCONFIG_HAVE_PATA_PLATFORM[0m
select [31mCONFIG_ISA_DMA_API[0m
select [31mCONFIG_NEED_MACH_IO_H[0m
select [31mCONFIG_NEED_MACH_MEMORY_H[0m
select [31mCONFIG_NO_IOPORT_MAP[0m
help
On the Acorn Risc-PC, Linux can support the internal [31mCONFIG_IDE[0m disk and
CD-[31mCONFIG_ROM[0m interface, serial and parallel port, and the floppy drive.
config [31mCONFIG_ARCH_SA1100[0m
bool "SA1100-based"
select [31mCONFIG_ARCH_MTD_XIP[0m
select [31mCONFIG_ARCH_SPARSEMEM_ENABLE[0m
select [31mCONFIG_CLKDEV_LOOKUP[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_CLKSRC_PXA[0m
select [31mCONFIG_TIMER_OF[0m if [31mCONFIG_OF[0m
select [31mCONFIG_COMMON_CLK[0m
select [31mCONFIG_CPU_FREQ[0m
select [31mCONFIG_CPU_SA1100[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_HAVE_IDE[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_ISA[0m
select [31mCONFIG_NEED_MACH_MEMORY_H[0m
select [31mCONFIG_SPARSE_IRQ[0m
help
Support for StrongARM 11x0 based boards.
config [31mCONFIG_ARCH_S3C24XX[0m
bool "Samsung S3C24XX SoCs"
select [31mCONFIG_ATAGS[0m
select [31mCONFIG_CLKDEV_LOOKUP[0m
select [31mCONFIG_CLKSRC_SAMSUNG_PWM[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_GPIO_SAMSUNG[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select [31mCONFIG_HAVE_S3C2410_I2C[0m if [31mCONFIG_I2C[0m
select [31mCONFIG_HAVE_S3C2410_WATCHDOG[0m if [31mCONFIG_WATCHDOG[0m
select [31mCONFIG_HAVE_S3C_RTC[0m if [31mCONFIG_RTC_CLASS[0m
select [31mCONFIG_NEED_MACH_IO_H[0m
select [31mCONFIG_SAMSUNG_ATAGS[0m
select [31mCONFIG_USE_OF[0m
help
Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
(<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
Samsung SMDK2410 development board (and derivatives).
config [31mCONFIG_ARCH_OMAP1[0m
bool "TI OMAP1"
depends on [31mCONFIG_MMU[0m
select [31mCONFIG_ARCH_HAS_HOLES_MEMORYMODEL[0m
select [31mCONFIG_ARCH_OMAP[0m
select [31mCONFIG_CLKDEV_LOOKUP[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_HAVE_IDE[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_NEED_MACH_IO_H[0m if [31mCONFIG_PCCARD[0m
select [31mCONFIG_NEED_MACH_MEMORY_H[0m
select [31mCONFIG_SPARSE_IRQ[0m
help
Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
endchoice
menu "Multiple platform selection"
depends on [31mCONFIG_ARCH_MULTIPLATFORM[0m
comment "CPU Core family selection"
config [31mCONFIG_ARCH_MULTI_V4[0m
bool "ARMv4 based platforms (FA526)"
depends on ![31mCONFIG_ARCH_MULTI_V6_V7[0m
select [31mCONFIG_ARCH_MULTI_V4_V5[0m
select [31mCONFIG_CPU_FA526[0m
config [31mCONFIG_ARCH_MULTI_V4T[0m
bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
depends on ![31mCONFIG_ARCH_MULTI_V6_V7[0m
select [31mCONFIG_ARCH_MULTI_V4_V5[0m
select [31mCONFIG_CPU_ARM920T[0m if !([31mCONFIG_CPU_ARM7TDMI[0m || [31mCONFIG_CPU_ARM720T[0m || \
[31mCONFIG_CPU_ARM740T[0m || [31mCONFIG_CPU_ARM9TDMI[0m || [31mCONFIG_CPU_ARM922T[0m || \
[31mCONFIG_CPU_ARM925T[0m || [31mCONFIG_CPU_ARM940T[0m)
config [31mCONFIG_ARCH_MULTI_V5[0m
bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
depends on ![31mCONFIG_ARCH_MULTI_V6_V7[0m
select [31mCONFIG_ARCH_MULTI_V4_V5[0m
select [31mCONFIG_CPU_ARM926T[0m if !([31mCONFIG_CPU_ARM946E[0m || [31mCONFIG_CPU_ARM1020[0m || \
[31mCONFIG_CPU_ARM1020E[0m || [31mCONFIG_CPU_ARM1022[0m || [31mCONFIG_CPU_ARM1026[0m || \
[31mCONFIG_CPU_XSCALE[0m || [31mCONFIG_CPU_XSC3[0m || [31mCONFIG_CPU_MOHAWK[0m || [31mCONFIG_CPU_FEROCEON[0m)
config [31mCONFIG_ARCH_MULTI_V4_V5[0m
bool
config [31mCONFIG_ARCH_MULTI_V6[0m
bool "ARMv6 based platforms (ARM11)"
select [31mCONFIG_ARCH_MULTI_V6_V7[0m
select [31mCONFIG_CPU_V6K[0m
config [31mCONFIG_ARCH_MULTI_V7[0m
bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
default y
select [31mCONFIG_ARCH_MULTI_V6_V7[0m
select [31mCONFIG_CPU_V7[0m
select [31mCONFIG_HAVE_SMP[0m
config [31mCONFIG_ARCH_MULTI_V6_V7[0m
bool
select [31mCONFIG_MIGHT_HAVE_CACHE_L2X0[0m
config [31mCONFIG_ARCH_MULTI_CPU_AUTO[0m
def_bool !([31mCONFIG_ARCH_MULTI_V4[0m || [31mCONFIG_ARCH_MULTI_V4T[0m || [31mCONFIG_ARCH_MULTI_V6_V7[0m)
select [31mCONFIG_ARCH_MULTI_V5[0m
endmenu
config [31mCONFIG_ARCH_VIRT[0m
bool "Dummy Virtual Machine"
depends on [31mCONFIG_ARCH_MULTI_V7[0m
select [31mCONFIG_ARM_AMBA[0m
select [31mCONFIG_ARM_GIC[0m
select [31mCONFIG_ARM_GIC_V2M[0m if [31mCONFIG_PCI[0m
select [31mCONFIG_ARM_GIC_V3[0m
select [31mCONFIG_ARM_GIC_V3_ITS[0m if [31mCONFIG_PCI[0m
select [31mCONFIG_ARM_PSCI[0m
select [31mCONFIG_HAVE_ARM_ARCH_TIMER[0m
select [31mCONFIG_ARCH_SUPPORTS_BIG_ENDIAN[0m
#
# This is sorted alphabetically by mach-* pathname. However, plat-*
# Kconfigs may be included either alphabetically (according to the
# plat- suffix) or along side the corresponding mach-* source.
#
source "arch/arm/mach-actions/Kconfig"
source "arch/arm/mach-alpine/Kconfig"
source "arch/arm/mach-artpec/Kconfig"
source "arch/arm/mach-asm9260/Kconfig"
source "arch/arm/mach-aspeed/Kconfig"
source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-axxia/Kconfig"
source "arch/arm/mach-bcm/Kconfig"
source "arch/arm/mach-berlin/Kconfig"
source "arch/arm/mach-clps711x/Kconfig"
source "arch/arm/mach-cns3xxx/Kconfig"
source "arch/arm/mach-davinci/Kconfig"
source "arch/arm/mach-digicolor/Kconfig"
source "arch/arm/mach-dove/Kconfig"
source "arch/arm/mach-ep93xx/Kconfig"
source "arch/arm/mach-exynos/Kconfig"
source "arch/arm/plat-samsung/Kconfig"
source "arch/arm/mach-footbridge/Kconfig"
source "arch/arm/mach-gemini/Kconfig"
source "arch/arm/mach-highbank/Kconfig"
source "arch/arm/mach-hisi/Kconfig"
source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-integrator/Kconfig"
source "arch/arm/mach-iop32x/Kconfig"
source "arch/arm/mach-ixp4xx/Kconfig"
source "arch/arm/mach-keystone/Kconfig"
source "arch/arm/mach-lpc32xx/Kconfig"
source "arch/arm/mach-mediatek/Kconfig"
source "arch/arm/mach-meson/Kconfig"
source "arch/arm/mach-milbeaut/Kconfig"
source "arch/arm/mach-mmp/Kconfig"
source "arch/arm/mach-moxart/Kconfig"
source "arch/arm/mach-mv78xx0/Kconfig"
source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/mach-mxs/Kconfig"
source "arch/arm/mach-nomadik/Kconfig"
source "arch/arm/mach-npcm/Kconfig"
source "arch/arm/mach-nspire/Kconfig"
source "arch/arm/plat-omap/Kconfig"
source "arch/arm/mach-omap1/Kconfig"
source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/mach-oxnas/Kconfig"
source "arch/arm/mach-picoxcell/Kconfig"
source "arch/arm/mach-prima2/Kconfig"
source "arch/arm/mach-pxa/Kconfig"
source "arch/arm/plat-pxa/Kconfig"
source "arch/arm/mach-qcom/Kconfig"
source "arch/arm/mach-rda/Kconfig"
source "arch/arm/mach-realview/Kconfig"
source "arch/arm/mach-rockchip/Kconfig"
source "arch/arm/mach-s3c24xx/Kconfig"
source "arch/arm/mach-s3c64xx/Kconfig"
source "arch/arm/mach-s5pv210/Kconfig"
source "arch/arm/mach-sa1100/Kconfig"
source "arch/arm/mach-shmobile/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"
source "arch/arm/mach-spear/Kconfig"
source "arch/arm/mach-sti/Kconfig"
source "arch/arm/mach-stm32/Kconfig"
source "arch/arm/mach-sunxi/Kconfig"
source "arch/arm/mach-tango/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/mach-u300/Kconfig"
source "arch/arm/mach-uniphier/Kconfig"
source "arch/arm/mach-ux500/Kconfig"
source "arch/arm/mach-versatile/Kconfig"
source "arch/arm/mach-vexpress/Kconfig"
source "arch/arm/plat-versatile/Kconfig"
source "arch/arm/mach-vt8500/Kconfig"
source "arch/arm/mach-zx/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
# ARMv7-[31mCONFIG_M[0m architecture
config [31mCONFIG_ARCH_EFM32[0m
bool "Energy Micro efm32"
depends on [31mCONFIG_ARM_SINGLE_ARMV7M[0m
select [31mCONFIG_GPIOLIB[0m
help
Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
processors.
config [31mCONFIG_ARCH_LPC18XX[0m
bool "NXP LPC18xx/LPC43xx"
depends on [31mCONFIG_ARM_SINGLE_ARMV7M[0m
select [31mCONFIG_ARCH_HAS_RESET_CONTROLLER[0m
select [31mCONFIG_ARM_AMBA[0m
select [31mCONFIG_CLKSRC_LPC32XX[0m
select [31mCONFIG_PINCTRL[0m
help
Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
high performance microcontrollers.
config [31mCONFIG_ARCH_MPS2[0m
bool "ARM MPS2 platform"
depends on [31mCONFIG_ARM_SINGLE_ARMV7M[0m
select [31mCONFIG_ARM_AMBA[0m
select [31mCONFIG_CLKSRC_MPS2[0m
help
Support for Cortex-[31mCONFIG_M[0m Prototyping System (or V2M-MPS2) which comes
with a range of available cores like Cortex-M3/M4/M7.
Please, note that depends which Application Note is used memory map
for the platform may vary, so adjustment of RAM base might be needed.
# Definitions to make life easier
config [31mCONFIG_ARCH_ACORN[0m
bool
config [31mCONFIG_PLAT_IOP[0m
bool
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
config [31mCONFIG_PLAT_ORION[0m
bool
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_COMMON_CLK[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_PLAT_ORION_LEGACY[0m
bool
select [31mCONFIG_PLAT_ORION[0m
config [31mCONFIG_PLAT_PXA[0m
bool
config [31mCONFIG_PLAT_VERSATILE[0m
bool
source "arch/arm/mm/Kconfig"
config [31mCONFIG_IWMMXT[0m
bool "Enable iWMMXt support"
depends on [31mCONFIG_CPU_XSCALE[0m || [31mCONFIG_CPU_XSC3[0m || [31mCONFIG_CPU_MOHAWK[0m || [31mCONFIG_CPU_PJ4[0m || [31mCONFIG_CPU_PJ4B[0m
default y if [31mCONFIG_PXA27x[0m || [31mCONFIG_PXA3xx[0m || [31mCONFIG_ARCH_MMP[0m || [31mCONFIG_CPU_PJ4[0m || [31mCONFIG_CPU_PJ4B[0m
help
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
if ![31mCONFIG_MMU[0m
source "arch/arm/Kconfig-nommu"
endif
config [31mCONFIG_PJ4B_ERRATA_4742[0m
bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
depends on [31mCONFIG_CPU_PJ4B[0m && [31mCONFIG_MACH_ARMADA_370[0m
default y
help
When coming out of either a Wait for Interrupt (WFI) or a Wait for
Event (WFE) IDLE states, a specific timing sensitivity exists between
the retiring WFI/WFE instructions and the newly issued subsequent
instructions. This sensitivity can result in a CPU hang scenario.
Workaround:
The software must insert either a Data Synchronization Barrier (DSB)
or Data Memory Barrier (DMB) command immediately after the WFI/WFE
instruction
config [31mCONFIG_ARM_ERRATA_326103[0m
bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
depends on [31mCONFIG_CPU_V6[0m
help
Executing a SWP instruction to read-only memory does not set bit 11
of the FSR on the [31mCONFIG_ARM[0m 1136 prior to r1p0. This causes the kernel to
treat the access as a read, preventing a COW from occurring and
causing the faulting task to livelock.
config [31mCONFIG_ARM_ERRATA_411920[0m
bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
depends on [31mCONFIG_CPU_V6[0m || [31mCONFIG_CPU_V6K[0m
help
Invalidation of the Instruction Cache operation can
fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
It does not affect the MPCore. This option enables the [31mCONFIG_ARM[0m Ltd.
recommended workaround.
config [31mCONFIG_ARM_ERRATA_430973[0m
bool "ARM errata: Stale prediction on replaced interworking branch"
depends on [31mCONFIG_CPU_V7[0m
help
This option enables the workaround for the 430973 Cortex-A8
r1p* erratum. If a code sequence containing an [31mCONFIG_ARM[0m/Thumb
interworking branch is replaced with another code sequence at the
same virtual address, whether due to self-modifying code or virtual
to physical address re-mapping, Cortex-A8 does not recover from the
stale interworking branch prediction. This results in Cortex-A8
executing the new code sequence in the incorrect [31mCONFIG_ARM[0m or Thumb state.
The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
and also flushes the branch target cache at every context switch.
Note that setting specific bits in the ACTLR register may not be
available in non-secure mode.
config [31mCONFIG_ARM_ERRATA_458693[0m
bool "ARM errata: Processor deadlock when a false hazard is created"
depends on [31mCONFIG_CPU_V7[0m
depends on ![31mCONFIG_ARCH_MULTIPLATFORM[0m
help
This option enables the workaround for the 458693 Cortex-A8 (r2p0)
erratum. For very specific sequences of memory operations, it is
possible for a hazard condition intended for a cache line to instead
be incorrectly associated with a different cache line. This false
hazard might then cause a processor deadlock. The workaround enables
the L1 caching of the [31mCONFIG_NEON[0m accesses and disables the PLD instruction
in the ACTLR register. Note that setting specific bits in the ACTLR
register may not be available in non-secure mode.
config [31mCONFIG_ARM_ERRATA_460075[0m
bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
depends on [31mCONFIG_CPU_V7[0m
depends on ![31mCONFIG_ARCH_MULTIPLATFORM[0m
help
This option enables the workaround for the 460075 Cortex-A8 (r2p0)
erratum. Any asynchronous access to the L2 cache may encounter a
situation in which recent store transactions to the L2 cache are lost
and overwritten with stale memory contents from external memory. The
workaround disables the write-allocate mode for the L2 cache via the
ACTLR register. Note that setting specific bits in the ACTLR register
may not be available in non-secure mode.
config [31mCONFIG_ARM_ERRATA_742230[0m
bool "ARM errata: DMB operation may be faulty"
depends on [31mCONFIG_CPU_V7[0m && [31mCONFIG_SMP[0m
depends on ![31mCONFIG_ARCH_MULTIPLATFORM[0m
help
This option enables the workaround for the 742230 Cortex-A9
(r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
between two write operations may not ensure the correct visibility
ordering of the two writes. This workaround sets a specific bit in
the diagnostic register of the Cortex-A9 which causes the DMB
instruction to behave as a DSB, ensuring the correct behaviour of
the two writes.
config [31mCONFIG_ARM_ERRATA_742231[0m
bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
depends on [31mCONFIG_CPU_V7[0m && [31mCONFIG_SMP[0m
depends on ![31mCONFIG_ARCH_MULTIPLATFORM[0m
help
This option enables the workaround for the 742231 Cortex-A9
(r2p0..r2p2) erratum. Under certain conditions, specific to the
Cortex-A9 MPCore micro-architecture, two CPUs working in [31mCONFIG_SMP[0m mode,
accessing some data located in the same cache line, may get corrupted
data due to bad handling of the address hazard when the line gets
replaced from one of the CPUs at the same time as another CPU is
accessing it. This workaround sets specific bits in the diagnostic
register of the Cortex-A9 which reduces the linefill issuing
capabilities of the processor.
config [31mCONFIG_ARM_ERRATA_643719[0m
bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
depends on [31mCONFIG_CPU_V7[0m && [31mCONFIG_SMP[0m
default y
help
This option enables the workaround for the 643719 Cortex-A9 (prior to
r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
register returns zero when it should return one. The workaround
corrects this value, ensuring cache maintenance operations which use
it behave as intended and avoiding data corruption.
config [31mCONFIG_ARM_ERRATA_720789[0m
bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
depends on [31mCONFIG_CPU_V7[0m
help
This option enables the workaround for the 720789 Cortex-A9 (prior to
r2p0) erratum. [31mCONFIG_A[0m faulty ASID can be sent to the other CPUs for the
broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
As a consequence of this erratum, some TLB entries which should be
invalidated are not, resulting in an incoherency in the system page
tables. The workaround changes the TLB flushing routines to invalidate
entries regardless of the ASID.
config [31mCONFIG_ARM_ERRATA_743622[0m
bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
depends on [31mCONFIG_CPU_V7[0m
depends on ![31mCONFIG_ARCH_MULTIPLATFORM[0m
help
This option enables the workaround for the 743622 Cortex-A9
(r2p*) erratum. Under very rare conditions, a faulty
optimisation in the Cortex-A9 Store Buffer may lead to data
corruption. This workaround sets a specific bit in the diagnostic
register of the Cortex-A9 which disables the Store Buffer
optimisation, preventing the defect from occurring. This has no
visible impact on the overall performance or power consumption of the
processor.
config [31mCONFIG_ARM_ERRATA_751472[0m
bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
depends on [31mCONFIG_CPU_V7[0m
depends on ![31mCONFIG_ARCH_MULTIPLATFORM[0m
help
This option enables the workaround for the 751472 Cortex-A9 (prior
to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
completion of a following broadcasted operation if the second
operation is received by a CPU before the ICIALLUIS has completed,
potentially leading to corrupted entries in the cache or TLB.
config [31mCONFIG_ARM_ERRATA_754322[0m
bool "ARM errata: possible faulty MMU translations following an ASID switch"
depends on [31mCONFIG_CPU_V7[0m
help
This option enables the workaround for the 754322 Cortex-A9 (r2p*,
r3p*) erratum. [31mCONFIG_A[0m speculative memory access may cause a page table walk
which starts prior to an ASID switch but completes afterwards. This
can populate the micro-TLB with a stale entry which may be hit with
the new ASID. This workaround places two dsb instructions in the mm
switching code so that no page table walks can cross the ASID switch.
config [31mCONFIG_ARM_ERRATA_754327[0m
bool "ARM errata: no automatic Store Buffer drain"
depends on [31mCONFIG_CPU_V7[0m && [31mCONFIG_SMP[0m
help
This option enables the workaround for the 754327 Cortex-A9 (prior to
r2p0) erratum. The Store Buffer does not have any automatic draining
mechanism and therefore a livelock may occur if an external agent
continuously polls a memory location waiting to observe an update.
This workaround defines cpu_relax() as smp_mb(), preventing correctly
written polling loops from denying visibility of updates to memory.
config [31mCONFIG_ARM_ERRATA_364296[0m
bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
depends on [31mCONFIG_CPU_V6[0m
help
This options enables the workaround for the 364296 ARM1136
r0p2 erratum (possible cache data corruption with
hit-under-miss enabled). It sets the undocumented bit 31 in
the auxiliary control register and the FI bit in the control
register, thus disabling hit-under-miss without putting the
processor into full low interrupt latency mode. ARM11MPCore
is not affected.
config [31mCONFIG_ARM_ERRATA_764369[0m
bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
depends on [31mCONFIG_CPU_V7[0m && [31mCONFIG_SMP[0m
help
This option enables the workaround for erratum 764369
affecting Cortex-A9 MPCore with two or more processors (all
current revisions). Under certain timing circumstances, a data
cache line maintenance operation by MVA targeting an Inner
Shareable memory region may fail to proceed up to either the
Point of Coherency or to the Point of Unification of the
system. This workaround adds a DSB instruction before the
relevant cache maintenance functions and sets a specific bit
in the diagnostic control register of the SCU.
config [31mCONFIG_ARM_ERRATA_775420[0m
bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
depends on [31mCONFIG_CPU_V7[0m
help
This option enables the workaround for the 775420 Cortex-A9 (r2p2,
r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
operation aborts with [31mCONFIG_MMU[0m exception, it might cause the processor
to deadlock. This workaround puts DSB before executing ISB if
an abort may occur on cache maintenance.
config [31mCONFIG_ARM_ERRATA_798181[0m
bool "ARM errata: TLBI/DSB failure on Cortex-A15"
depends on [31mCONFIG_CPU_V7[0m && [31mCONFIG_SMP[0m
help
On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
adequately shooting down all use of the old entries. This
option enables the Linux kernel workaround for this erratum
which sends an IPI to the CPUs that are running the same ASID
as the one being invalidated.
config [31mCONFIG_ARM_ERRATA_773022[0m
bool "ARM errata: incorrect instructions may be executed from loop buffer"
depends on [31mCONFIG_CPU_V7[0m
help
This option enables the workaround for the 773022 Cortex-A15
(up to r0p4) erratum. In certain rare sequences of code, the
loop buffer may deliver incorrect instructions. This
workaround disables the loop buffer to avoid the erratum.
config [31mCONFIG_ARM_ERRATA_818325_852422[0m
bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
depends on [31mCONFIG_CPU_V7[0m
help
This option enables the workaround for:
- Cortex-A12 818325: Execution of an UNPREDICTABLE STR or [31mCONFIG_STM[0m
instruction might deadlock. Fixed in r0p1.
- Cortex-A12 852422: Execution of a sequence of instructions might
lead to either a data corruption or a CPU deadlock. Not fixed in
any Cortex-A12 cores yet.
This workaround for all both errata involves setting bit[12] of the
Feature Register. This bit disables an optimisation applied to a
sequence of 2 instructions that use opposing condition codes.
config [31mCONFIG_ARM_ERRATA_821420[0m
bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
depends on [31mCONFIG_CPU_V7[0m
help
This option enables the workaround for the 821420 Cortex-A12
(all revs) erratum. In very rare timing conditions, a sequence
of VMOV to Core registers instructions, for which the second
one is in the shadow of a branch or abort, can lead to a
deadlock when the VMOV instructions are issued out-of-order.
config [31mCONFIG_ARM_ERRATA_825619[0m
bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
depends on [31mCONFIG_CPU_V7[0m
help
This option enables the workaround for the 825619 Cortex-A12
(all revs) erratum. Within rare timing constraints, executing a
DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
and Device/Strongly-Ordered loads and stores might cause deadlock
config [31mCONFIG_ARM_ERRATA_857271[0m
bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
depends on [31mCONFIG_CPU_V7[0m
help
This option enables the workaround for the 857271 Cortex-A12
(all revs) erratum. Under very rare timing conditions, the CPU might
hang. The workaround is expected to have a < 1% performance impact.
config [31mCONFIG_ARM_ERRATA_852421[0m
bool "ARM errata: A17: DMB ST might fail to create order between stores"
depends on [31mCONFIG_CPU_V7[0m
help
This option enables the workaround for the 852421 Cortex-A17
(r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
execution of a DMB ST instruction might fail to properly order
stores from GroupA and stores from GroupB.
config [31mCONFIG_ARM_ERRATA_852423[0m
bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
depends on [31mCONFIG_CPU_V7[0m
help
This option enables the workaround for:
- Cortex-A17 852423: Execution of a sequence of instructions might
lead to either a data corruption or a CPU deadlock. Not fixed in
any Cortex-A17 cores yet.
This is identical to Cortex-A12 erratum 852422. It is a separate
config option from the A12 erratum due to the way errata are checked
for and handled.
config [31mCONFIG_ARM_ERRATA_857272[0m
bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
depends on [31mCONFIG_CPU_V7[0m
help
This option enables the workaround for the 857272 Cortex-A17 erratum.
This erratum is not known to be fixed in any A17 revision.
This is identical to Cortex-A12 erratum 857271. It is a separate
config option from the A12 erratum due to the way errata are checked
for and handled.
endmenu
source "arch/arm/common/Kconfig"
menu "Bus support"
config [31mCONFIG_ISA[0m
bool
help
Find out whether you have [31mCONFIG_ISA[0m slots on your motherboard. [31mCONFIG_ISA[0m is the
name of a bus system, i.e. the way the CPU talks to the other stuff
inside your box. Other bus systems are [31mCONFIG_PCI[0m, [31mCONFIG_EISA[0m, MicroChannel
([31mCONFIG_MCA[0m) or VESA. [31mCONFIG_ISA[0m is an older system, now being displaced by [31mCONFIG_PCI[0m;
newer boards don't support it. If you have [31mCONFIG_ISA[0m, say Y, otherwise N.
# Select [31mCONFIG_ISA[0m DMA controller support
config [31mCONFIG_ISA_DMA[0m
bool
select [31mCONFIG_ISA_DMA_API[0m
# Select [31mCONFIG_ISA[0m DMA interface
config [31mCONFIG_ISA_DMA_API[0m
bool
config [31mCONFIG_PCI_NANOENGINE[0m
bool "BSE nanoEngine PCI support"
depends on [31mCONFIG_SA1100_NANOENGINE[0m
help
Enable [31mCONFIG_PCI[0m on the BSE nanoEngine board.
config [31mCONFIG_PCI_HOST_ITE8152[0m
bool
depends on [31mCONFIG_PCI[0m && [31mCONFIG_MACH_ARMCORE[0m
default y
select [31mCONFIG_DMABOUNCE[0m
config [31mCONFIG_ARM_ERRATA_814220[0m
bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
depends on [31mCONFIG_CPU_V7[0m
help
The v7 [31mCONFIG_ARM[0m states that all cache and branch predictor maintenance
operations that do not specify an address execute, relative to
each other, in program order.
However, because of this erratum, an L2 set/way cache maintenance
operation can overtake an L1 set/way cache maintenance operation.
This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
r0p4, r0p5.
endmenu
menu "Kernel Features"
config [31mCONFIG_HAVE_SMP[0m
bool
help
This option should be selected by machines which have an [31mCONFIG_SMP[0m-
capable CPU.
The only effect of this option is to make the [31mCONFIG_SMP[0m-related
options available to the user for configuration.
config [31mCONFIG_SMP[0m
bool "Symmetric Multi-Processing"
depends on [31mCONFIG_CPU_V6K[0m || [31mCONFIG_CPU_V7[0m
depends on [31mCONFIG_GENERIC_CLOCKEVENTS[0m
depends on [31mCONFIG_HAVE_SMP[0m
depends on [31mCONFIG_MMU[0m || [31mCONFIG_ARM_MPU[0m
select [31mCONFIG_IRQ_WORK[0m
help
This enables support for systems with more than one CPU. If you have
a system with only one CPU, say N. If you have a system with more
than one CPU, say Y.
If you say N here, the kernel will run on uni- and multiprocessor
machines, but will use only one CPU of a multiprocessor machine. If
you say Y here, the kernel will run on many, but not all,
uniprocessor machines. On a uniprocessor machine, the kernel
will run faster if you say N here.
See also <file:Documentation/x86/i386/IO-APIC.rst>,
<file:Documentation/admin-guide/lockup-watchdogs.rst> and the [31mCONFIG_SMP[0m-HOWTO available at
<http://tldp.org/HOWTO/SMP-HOWTO.html>.
If you don't know what to do here, say N.
config [31mCONFIG_SMP_ON_UP[0m
bool "Allow booting SMP kernel on uniprocessor systems"
depends on [31mCONFIG_SMP[0m && ![31mCONFIG_XIP_KERNEL[0m && [31mCONFIG_MMU[0m
default y
help
[31mCONFIG_SMP[0m kernels contain instructions which fail on non-[31mCONFIG_SMP[0m processors.
Enabling this option allows the kernel to modify itself to make
these instructions safe. Disabling it allows about 1K of space
savings.
If you don't know what to do here, say Y.
config [31mCONFIG_ARM_CPU_TOPOLOGY[0m
bool "Support cpu topology definition"
depends on [31mCONFIG_SMP[0m && [31mCONFIG_CPU_V7[0m
default y
help
Support [31mCONFIG_ARM[0m cpu topology definition. The MPIDR register defines
affinity between processors which is then used to describe the cpu
topology of an [31mCONFIG_ARM[0m System.
config [31mCONFIG_SCHED_MC[0m
bool "Multi-core scheduler support"
depends on [31mCONFIG_ARM_CPU_TOPOLOGY[0m
help
Multi-core scheduler support improves the CPU scheduler's decision
making when dealing with multi-core CPU chips at a cost of slightly
increased overhead in some places. If unsure say N here.
config [31mCONFIG_SCHED_SMT[0m
bool "SMT scheduler support"
depends on [31mCONFIG_ARM_CPU_TOPOLOGY[0m
help
Improves the CPU scheduler's decision making when dealing with
MultiThreading at a cost of slightly increased overhead in some
places. If unsure say N here.
config [31mCONFIG_HAVE_ARM_SCU[0m
bool
help
This option enables support for the [31mCONFIG_ARM[0m snoop control unit
config [31mCONFIG_HAVE_ARM_ARCH_TIMER[0m
bool "Architected timer support"
depends on [31mCONFIG_CPU_V7[0m
select [31mCONFIG_ARM_ARCH_TIMER[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
help
This option enables support for the [31mCONFIG_ARM[0m architected timer
config [31mCONFIG_HAVE_ARM_TWD[0m
bool
help
This options enables support for the [31mCONFIG_ARM[0m timer and watchdog unit
config [31mCONFIG_MCPM[0m
bool "Multi-Cluster Power Management"
depends on [31mCONFIG_CPU_V7[0m && [31mCONFIG_SMP[0m
help
This option provides the common power management infrastructure
for (multi-)cluster based systems, such as big.LITTLE based
systems.
config [31mCONFIG_MCPM_QUAD_CLUSTER[0m
bool
depends on [31mCONFIG_MCPM[0m
help
To avoid wasting resources unnecessarily, [31mCONFIG_MCPM[0m only supports up
to 2 clusters by default.
Platforms with 3 or 4 clusters that use [31mCONFIG_MCPM[0m must select this
option to allow the additional clusters to be managed.
config [31mCONFIG_BIG_LITTLE[0m
bool "big.LITTLE support (Experimental)"
depends on [31mCONFIG_CPU_V7[0m && [31mCONFIG_SMP[0m
select [31mCONFIG_MCPM[0m
help
This option enables support selections for the big.LITTLE
system architecture.
config [31mCONFIG_BL_SWITCHER[0m
bool "big.LITTLE switcher support"
depends on [31mCONFIG_BIG_LITTLE[0m && [31mCONFIG_MCPM[0m && [31mCONFIG_HOTPLUG_CPU[0m && [31mCONFIG_ARM_GIC[0m
select [31mCONFIG_CPU_PM[0m
help
The big.LITTLE "switcher" provides the core functionality to
transparently handle transition between a cluster of A15's
and a cluster of A7's in a big.LITTLE system.
config [31mCONFIG_BL_SWITCHER_DUMMY_IF[0m
tristate "Simple big.LITTLE switcher user interface"
depends on [31mCONFIG_BL_SWITCHER[0m && [31mCONFIG_DEBUG_KERNEL[0m
help
This is a simple and dummy char dev interface to control
the big.LITTLE switcher core code. It is meant for
debugging purposes only.
choice
prompt "Memory split"
depends on [31mCONFIG_MMU[0m
default [31mCONFIG_VMSPLIT_3G[0m
help
Select the desired split between kernel and user memory.
If you are not absolutely sure what you are doing, leave this
option alone!
config [31mCONFIG_VMSPLIT_3G[0m
bool "3G/1G user/kernel split"
config [31mCONFIG_VMSPLIT_3G_OPT[0m
depends on ![31mCONFIG_ARM_LPAE[0m
bool "3G/1G user/kernel split (for full 1G low memory)"
config [31mCONFIG_VMSPLIT_2G[0m
bool "2G/2G user/kernel split"
config [31mCONFIG_VMSPLIT_1G[0m
bool "1G/3G user/kernel split"
endchoice
config [31mCONFIG_PAGE_OFFSET[0m
hex
default [31mCONFIG_PHYS_OFFSET[0m if ![31mCONFIG_MMU[0m
default 0x40000000 if [31mCONFIG_VMSPLIT_1G[0m
default 0x80000000 if [31mCONFIG_VMSPLIT_2G[0m
default 0xB0000000 if [31mCONFIG_VMSPLIT_3G_OPT[0m
default 0xC0000000
config [31mCONFIG_NR_CPUS[0m
int "Maximum number of CPUs (2-32)"
range 2 32
depends on [31mCONFIG_SMP[0m
default "4"
config [31mCONFIG_HOTPLUG_CPU[0m
bool "Support for hot-pluggable CPUs"
depends on [31mCONFIG_SMP[0m
select [31mCONFIG_GENERIC_IRQ_MIGRATION[0m
help
Say Y here to experiment with turning CPUs off and on. CPUs
can be controlled through /sys/devices/system/cpu.
config [31mCONFIG_ARM_PSCI[0m
bool "Support for the ARM Power State Coordination Interface (PSCI)"
depends on [31mCONFIG_HAVE_ARM_SMCCC[0m
select [31mCONFIG_ARM_PSCI_FW[0m
help
Say Y here if you want Linux to communicate with system firmware
implementing the PSCI specification for CPU-centric power
management operations described in [31mCONFIG_ARM[0m document number [31mCONFIG_ARM[0m DEN
0022A ("Power State Coordination Interface System Software on
ARM processors").
# The GPIO number here must be sorted by descending number. In case of
# a multiplatform kernel, we just want the highest value required by the
# selected platforms.
config [31mCONFIG_ARCH_NR_GPIO[0m
int
default 2048 if [31mCONFIG_ARCH_SOCFPGA[0m
default 1024 if [31mCONFIG_ARCH_BRCMSTB[0m || [31mCONFIG_ARCH_RENESAS[0m || [31mCONFIG_ARCH_TEGRA[0m || \
[31mCONFIG_ARCH_ZYNQ[0m
default 512 if [31mCONFIG_ARCH_EXYNOS[0m || [31mCONFIG_ARCH_KEYSTONE[0m || [31mCONFIG_SOC_OMAP5[0m || \
[31mCONFIG_SOC_DRA7XX[0m || [31mCONFIG_ARCH_S3C24XX[0m || [31mCONFIG_ARCH_S3C64XX[0m || [31mCONFIG_ARCH_S5PV210[0m
default 416 if [31mCONFIG_ARCH_SUNXI[0m
default 392 if [31mCONFIG_ARCH_U8500[0m
default 352 if [31mCONFIG_ARCH_VT8500[0m
default 288 if [31mCONFIG_ARCH_ROCKCHIP[0m
default 264 if [31mCONFIG_MACH_H4700[0m
default 0
help
Maximum number of GPIOs in the system.
If unsure, leave the default value.
config [31mCONFIG_HZ_FIXED[0m
int
default 200 if [31mCONFIG_ARCH_EBSA110[0m
default 128 if [31mCONFIG_SOC_AT91RM9200[0m
default 0
choice
depends on [31mCONFIG_HZ_FIXED[0m = 0
prompt "Timer frequency"
config [31mCONFIG_HZ_100[0m
bool "100 Hz"
config [31mCONFIG_HZ_200[0m
bool "200 Hz"
config [31mCONFIG_HZ_250[0m
bool "250 Hz"
config [31mCONFIG_HZ_300[0m
bool "300 Hz"
config [31mCONFIG_HZ_500[0m
bool "500 Hz"
config [31mCONFIG_HZ_1000[0m
bool "1000 Hz"
endchoice
config [31mCONFIG_HZ[0m
int
default [31mCONFIG_HZ_FIXED[0m if [31mCONFIG_HZ_FIXED[0m != 0
default 100 if [31mCONFIG_HZ_100[0m
default 200 if [31mCONFIG_HZ_200[0m
default 250 if [31mCONFIG_HZ_250[0m
default 300 if [31mCONFIG_HZ_300[0m
default 500 if [31mCONFIG_HZ_500[0m
default 1000
config [31mCONFIG_SCHED_HRTICK[0m
def_bool [31mCONFIG_HIGH_RES_TIMERS[0m
config [31mCONFIG_THUMB2_KERNEL[0m
bool "Compile the kernel in Thumb-2 mode" if ![31mCONFIG_CPU_THUMBONLY[0m
depends on ([31mCONFIG_CPU_V7[0m || [31mCONFIG_CPU_V7M[0m) && ![31mCONFIG_CPU_V6[0m && ![31mCONFIG_CPU_V6K[0m
default y if [31mCONFIG_CPU_THUMBONLY[0m
select [31mCONFIG_ARM_UNWIND[0m
help
By enabling this option, the kernel will be compiled in
Thumb-2 mode.
If unsure, say N.
config [31mCONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11[0m
bool "Work around buggy Thumb-2 short branch relocations in gas"
depends on [31mCONFIG_THUMB2_KERNEL[0m && [31mCONFIG_MODULES[0m
default y
help
Various binutils versions can resolve Thumb-2 branches to
locally-defined, preemptible global symbols as short-range "b.n"
branch instructions.
This is a problem, because there's no guarantee the final
destination of the symbol, or any candidate locations for a
trampoline, are within range of the branch. For this reason, the
kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
relocation in modules at all, and it makes little sense to add
support.
The symptom is that the kernel fails with an "unsupported
relocation" error when loading some modules.
Until fixed tools are available, passing
-fno-optimize-sibling-calls to gcc should prevent gcc generating
code which hits this problem, at the cost of a bit of extra runtime
stack usage in some cases.
The problem is described in more detail at:
https://bugs.launchpad.net/binutils-linaro/+bug/725126
Only Thumb-2 kernels are affected.
Unless you are sure your tools don't have this problem, say Y.
config [31mCONFIG_ARM_PATCH_IDIV[0m
bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
depends on [31mCONFIG_CPU_32v7[0m && ![31mCONFIG_XIP_KERNEL[0m
default y
help
The [31mCONFIG_ARM[0m compiler inserts calls to __aeabi_idiv() and
__aeabi_uidiv() when it needs to perform division on signed
and unsigned integers. Some v7 CPUs have support for the sdiv
and udiv instructions that can be used to implement those
functions.
Enabling this option allows the kernel to modify itself to
replace the first two instructions of these library functions
with the sdiv or udiv plus "bx lr" instructions when the CPU
it is running on supports them. Typically this will be faster
and less power intensive than running the original library
code to do integer division.
config [31mCONFIG_AEABI[0m
bool "Use the ARM EABI to compile the kernel" if ![31mCONFIG_CPU_V7[0m && \
![31mCONFIG_CPU_V7M[0m && ![31mCONFIG_CPU_V6[0m && ![31mCONFIG_CPU_V6K[0m && ![31mCONFIG_CC_IS_CLANG[0m
default [31mCONFIG_CPU_V7[0m || [31mCONFIG_CPU_V7M[0m || [31mCONFIG_CPU_V6[0m || [31mCONFIG_CPU_V6K[0m || [31mCONFIG_CC_IS_CLANG[0m
help
This option allows for the kernel to be compiled using the latest
[31mCONFIG_ARM[0m ABI (aka EABI). This is only useful if you are using a user
space environment that is also compiled with EABI.
Since there are major incompatibilities between the legacy ABI and
EABI, especially with regard to structure member alignment, this
option also changes the kernel syscall calling convention to
disambiguate both ABIs and allow for backward compatibility support
(selected with CONFIG_OABI_COMPAT).
To use this you need GCC version 4.0.0 or later.
config [31mCONFIG_OABI_COMPAT[0m
bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
depends on [31mCONFIG_AEABI[0m && ![31mCONFIG_THUMB2_KERNEL[0m
help
This option preserves the old syscall interface along with the
new ([31mCONFIG_ARM[0m EABI) one. It also provides a compatibility layer to
intercept syscalls that have structure arguments which layout
in memory differs between the legacy ABI and the new [31mCONFIG_ARM[0m EABI
(only for non "thumb" binaries). This option adds a tiny
overhead to all syscalls and produces a slightly larger kernel.
The seccomp filter system will not be available when this is
selected, since there is no way yet to sensibly distinguish
between calling conventions during filtering.
If you know you'll be using only pure EABI user space then you
can say N here. If this option is not selected and you attempt
to execute a legacy ABI binary then the result will be
UNPREDICTABLE (in fact it can be predicted that it won't work
at all). If in doubt say N.
config [31mCONFIG_ARCH_HAS_HOLES_MEMORYMODEL[0m
bool
config [31mCONFIG_ARCH_SPARSEMEM_ENABLE[0m
bool
config [31mCONFIG_ARCH_SPARSEMEM_DEFAULT[0m
def_bool [31mCONFIG_ARCH_SPARSEMEM_ENABLE[0m
config [31mCONFIG_HAVE_ARCH_PFN_VALID[0m
def_bool [31mCONFIG_ARCH_HAS_HOLES_MEMORYMODEL[0m || ![31mCONFIG_SPARSEMEM[0m
config [31mCONFIG_HIGHMEM[0m
bool "High Memory Support"
depends on [31mCONFIG_MMU[0m
help
The address space of [31mCONFIG_ARM[0m processors is only 4 Gigabytes large
and it has to accommodate user address space, kernel address
space as well as some memory mapped IO. That means that, if you
have a large amount of physical memory and/or IO, not all of the
memory can be "permanently mapped" by the kernel. The physical
memory that is not permanently mapped is called "high memory".
Depending on the selected kernel/user memory split, minimum
vmalloc space and actual amount of RAM, you may not need this
option which should result in a slightly faster kernel.
If unsure, say n.
config [31mCONFIG_HIGHPTE[0m
bool "Allocate 2nd-level pagetables from highmem" if [31mCONFIG_EXPERT[0m
depends on [31mCONFIG_HIGHMEM[0m
default y
help
The VM uses one page of physical memory for each page table.
For systems with a lot of processes, this can use a lot of
precious low memory, eventually leading to low memory being
consumed by page tables. Setting this option will allow
user-space 2nd level page tables to reside in high memory.
config [31mCONFIG_CPU_SW_DOMAIN_PAN[0m
bool "Enable use of CPU domains to implement privileged no-access"
depends on [31mCONFIG_MMU[0m && ![31mCONFIG_ARM_LPAE[0m
default y
help
Increase kernel security by ensuring that normal kernel accesses
are unable to access userspace addresses. This can help prevent
use-after-free bugs becoming an exploitable privilege escalation
by ensuring that magic values (such as LIST_POISON) will always
fault when dereferenced.
CPUs with low-vector mappings use a best-efforts implementation.
Their lower 1MB needs to remain accessible for the vectors, but
the remainder of userspace will become appropriately inaccessible.
config [31mCONFIG_HW_PERF_EVENTS[0m
def_bool y
depends on [31mCONFIG_ARM_PMU[0m
config [31mCONFIG_SYS_SUPPORTS_HUGETLBFS[0m
def_bool y
depends on [31mCONFIG_ARM_LPAE[0m
config [31mCONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE[0m
def_bool y
depends on [31mCONFIG_ARM_LPAE[0m
config [31mCONFIG_ARCH_WANT_GENERAL_HUGETLB[0m
def_bool y
config [31mCONFIG_ARM_MODULE_PLTS[0m
bool "Use PLTs to allow module memory to spill over into vmalloc area"
depends on [31mCONFIG_MODULES[0m
default y
help
Allocate PLTs when loading modules so that jumps and calls whose
targets are too far away for their relative offsets to be encoded
in the instructions themselves can be bounced via veneers in the
module's PLT. This allows modules to be allocated in the generic
vmalloc area after the dedicated module memory area has been
exhausted. The modules will use slightly more memory, but after
rounding up to page size, the actual memory footprint is usually
the same.
Disabling this is usually safe for small single-platform
configurations. If unsure, say y.
config [31mCONFIG_FORCE_MAX_ZONEORDER[0m
int "Maximum zone order"
default "12" if [31mCONFIG_SOC_AM33XX[0m
default "9" if [31mCONFIG_SA1111[0m || [31mCONFIG_ARCH_EFM32[0m
default "11"
help
The kernel memory allocator divides physically contiguous memory
blocks into "zones", where each zone is a power of two number of
pages. This option selects the largest power of two that the kernel
keeps in the memory allocator. If you need to allocate very large
blocks of physically contiguous memory, then you may need to
increase this value.
This config option is actually maximum order plus one. For example,
a value of 11 means that the largest free memory block is 2^10 pages.
config [31mCONFIG_ALIGNMENT_TRAP[0m
bool
depends on [31mCONFIG_CPU_CP15_MMU[0m
default y if ![31mCONFIG_ARCH_EBSA110[0m
select [31mCONFIG_HAVE_PROC_CPU[0m if [31mCONFIG_PROC_FS[0m
help
[31mCONFIG_ARM[0m processors cannot fetch/store information which is not
naturally aligned on the bus, i.e., a 4 byte fetch must start at an
address divisible by 4. On 32-bit [31mCONFIG_ARM[0m processors, these non-aligned
fetch/store instructions will be emulated in software if you say
here, which has a severe performance impact. This is necessary for
correct operation of some network protocols. With an IP-only
configuration it is safe to say N, otherwise say Y.
config [31mCONFIG_UACCESS_WITH_MEMCPY[0m
bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
depends on [31mCONFIG_MMU[0m
default y if [31mCONFIG_CPU_FEROCEON[0m
help
Implement faster copy_to_user and clear_user methods for CPU
cores where a 8-word [31mCONFIG_STM[0m instruction give significantly higher
memory write throughput than a sequence of individual 32bit stores.
[31mCONFIG_A[0m possible side effect is a slight increase in scheduling latency
between threads sharing the same address space if they invoke
such copy operations with large buffers.
However, if the CPU data cache is using a write-allocate mode,
this option is unlikely to provide any performance gain.
config [31mCONFIG_SECCOMP[0m
bool
prompt "Enable seccomp to safely compute untrusted bytecode"
---help---
This kernel feature is useful for number crunching applications
that may need to compute untrusted bytecode during their
execution. By using pipes or other transports made available to
the process as file descriptors supporting the read/write
syscalls, it's possible to isolate those applications in
their own address space using seccomp. Once seccomp is
enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
and the task is only allowed to execute a few safe syscalls
defined by each seccomp mode.
config [31mCONFIG_PARAVIRT[0m
bool "Enable paravirtualization code"
help
This changes the kernel so it can modify itself when it is run
under a hypervisor, potentially improving performance significantly
over full virtualization.
config [31mCONFIG_PARAVIRT_TIME_ACCOUNTING[0m
bool "Paravirtual steal time accounting"
select [31mCONFIG_PARAVIRT[0m
help
Select this option to enable fine granularity task steal time
accounting. Time spent executing other tasks in parallel with
the current vCPU is discounted from the vCPU power. To account for
that, there can be a small performance impact.
If in doubt, say N here.
config [31mCONFIG_XEN_DOM0[0m
def_bool y
depends on [31mCONFIG_XEN[0m
config [31mCONFIG_XEN[0m
bool "Xen guest support on ARM"
depends on [31mCONFIG_ARM[0m && [31mCONFIG_AEABI[0m && [31mCONFIG_OF[0m
depends on [31mCONFIG_CPU_V7[0m && ![31mCONFIG_CPU_V6[0m
depends on ![31mCONFIG_GENERIC_ATOMIC64[0m
depends on [31mCONFIG_MMU[0m
select [31mCONFIG_ARCH_DMA_ADDR_T_64BIT[0m
select [31mCONFIG_ARM_PSCI[0m
select [31mCONFIG_SWIOTLB[0m
select [31mCONFIG_SWIOTLB_XEN[0m
select [31mCONFIG_PARAVIRT[0m
help
Say Y if you want to run Linux in a Virtual Machine on Xen on [31mCONFIG_ARM[0m.
config [31mCONFIG_STACKPROTECTOR_PER_TASK[0m
bool "Use a unique stack canary value for each task"
depends on [31mCONFIG_GCC_PLUGINS[0m && [31mCONFIG_STACKPROTECTOR[0m && [31mCONFIG_SMP[0m && ![31mCONFIG_XIP_DEFLATED_DATA[0m
select [31mCONFIG_GCC_PLUGIN_ARM_SSP_PER_TASK[0m
default y
help
Due to the fact that GCC uses an ordinary symbol reference from
which to load the value of the stack canary, this value can only
change at reboot time on [31mCONFIG_SMP[0m systems, and all tasks running in the
kernel's address space are forced to use the same canary value for
the entire duration that the system is up.
Enable this option to switch to a different method that uses a
different canary value for each task.
endmenu
menu "Boot options"
config [31mCONFIG_USE_OF[0m
bool "Flattened Device Tree support"
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_OF[0m
help
Include support for flattened device tree machine descriptions.
config [31mCONFIG_ATAGS[0m
bool "Support for the traditional ATAGS boot data passing" if [31mCONFIG_USE_OF[0m
default y
help
This is the traditional way of passing data to the kernel at boot
time. If you are solely relying on the flattened device tree (or
the [31mCONFIG_ARM_ATAG_DTB_COMPAT[0m option) then you may unselect this option
to remove [31mCONFIG_ATAGS[0m support from your kernel binary. If unsure,
leave this to y.
config [31mCONFIG_DEPRECATED_PARAM_STRUCT[0m
bool "Provide old way to pass kernel parameters"
depends on [31mCONFIG_ATAGS[0m
help
This was deprecated in 2001 and announced to live on for 5 years.
Some old boot loaders still use this way.
# Compressed boot loader in [31mCONFIG_ROM[0m. Yes, we really want to ask about
# TEXT and BSS so we preserve their values in the config files.
config [31mCONFIG_ZBOOT_ROM_TEXT[0m
hex "Compressed ROM boot loader base address"
default "0"
help
The physical address at which the [31mCONFIG_ROM[0m-able zImage is to be
placed in the target. Platforms which normally make use of
[31mCONFIG_ROM[0m-able zImage formats normally set this to a suitable
value in their defconfig file.
If [31mCONFIG_ZBOOT_ROM[0m is not enabled, this has no effect.
config [31mCONFIG_ZBOOT_ROM_BSS[0m
hex "Compressed ROM boot loader BSS address"
default "0"
help
The base address of an area of read/write memory in the target
for the [31mCONFIG_ROM[0m-able zImage which must be available while the
decompressor is running. It must be large enough to hold the
entire decompressed kernel plus an additional 128 KiB.
Platforms which normally make use of [31mCONFIG_ROM[0m-able zImage formats
normally set this to a suitable value in their defconfig file.
If [31mCONFIG_ZBOOT_ROM[0m is not enabled, this has no effect.
config [31mCONFIG_ZBOOT_ROM[0m
bool "Compressed boot loader in ROM/flash"
depends on [31mCONFIG_ZBOOT_ROM_TEXT[0m != [31mCONFIG_ZBOOT_ROM_BSS[0m
depends on ![31mCONFIG_ARM_APPENDED_DTB[0m && ![31mCONFIG_XIP_KERNEL[0m && ![31mCONFIG_AUTO_ZRELADDR[0m
help
Say Y here if you intend to execute your compressed kernel image
(zImage) directly from [31mCONFIG_ROM[0m or flash. If unsure, say N.
config [31mCONFIG_ARM_APPENDED_DTB[0m
bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
depends on [31mCONFIG_OF[0m
help
With this option, the boot code will look for a device tree binary
(DTB) appended to zImage
(e.g. cat zImage <filename>.dtb > zImage_w_dtb).
This is meant as a backward compatibility convenience for those
systems with a bootloader that can't be upgraded to accommodate
the documented boot protocol using a device tree.
Beware that there is very little in terms of protection against
this option being confused by leftover garbage in memory that might
look like a DTB header after a reboot if no actual DTB is appended
to zImage. Do not leave this option active in a production kernel
if you don't intend to always append a DTB. Proper passing of the
location into r2 of a bootloader provided DTB is always preferable
to this option.
config [31mCONFIG_ARM_ATAG_DTB_COMPAT[0m
bool "Supplement the appended DTB with traditional ATAG information"
depends on [31mCONFIG_ARM_APPENDED_DTB[0m
help
Some old bootloaders can't be updated to a DTB capable one, yet
they provide ATAGs with memory configuration, the ramdisk address,
the kernel cmdline string, etc. Such information is dynamically
provided by the bootloader and can't always be stored in a static
DTB. To allow a device tree enabled kernel to be used with such
bootloaders, this option allows zImage to extract the information
from the ATAG list and store it at run time into the appended DTB.
choice
prompt "Kernel command line type" if [31mCONFIG_ARM_ATAG_DTB_COMPAT[0m
default [31mCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER[0m
config [31mCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER[0m
bool "Use bootloader kernel arguments if available"
help
Uses the command-line options passed by the boot loader instead of
the device tree bootargs property. If the boot loader doesn't provide
any, the device tree bootargs property will be used.
config [31mCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND[0m
bool "Extend with bootloader kernel arguments"
help
The command-line arguments provided by the boot loader will be
appended to the the device tree bootargs property.
endchoice
config [31mCONFIG_CMDLINE[0m
string "Default kernel command string"
default ""
help
On some architectures (EBSA110 and CATS), there is currently no way
for the boot loader to pass arguments to the kernel. For these
architectures, you should supply some command-line options at build
time by entering them here. As a minimum, you should specify the
memory size and the root device (e.g., mem=64M root=/dev/nfs).
choice
prompt "Kernel command line type" if [31mCONFIG_CMDLINE[0m != ""
default [31mCONFIG_CMDLINE_FROM_BOOTLOADER[0m
depends on [31mCONFIG_ATAGS[0m
config [31mCONFIG_CMDLINE_FROM_BOOTLOADER[0m
bool "Use bootloader kernel arguments if available"
help
Uses the command-line options passed by the boot loader. If
the boot loader doesn't provide any, the default kernel command
string provided in [31mCONFIG_CMDLINE[0m will be used.
config [31mCONFIG_CMDLINE_EXTEND[0m
bool "Extend bootloader kernel arguments"
help
The command-line arguments provided by the boot loader will be
appended to the default kernel command string.
config [31mCONFIG_CMDLINE_FORCE[0m
bool "Always use the default kernel command string"
help
Always use the default kernel command string, even if the boot
loader passes other arguments to the kernel.
This is useful if you cannot or don't want to change the
command-line options your boot loader passes to the kernel.
endchoice
config [31mCONFIG_XIP_KERNEL[0m
bool "Kernel Execute-In-Place from ROM"
depends on ![31mCONFIG_ARM_LPAE[0m && ![31mCONFIG_ARCH_MULTIPLATFORM[0m
help
Execute-In-Place allows the kernel to run from non-volatile storage
directly addressable by the CPU, such as NOR flash. This saves RAM
space since the text section of the kernel is not loaded from flash
to RAM. Read-write sections, such as the data section and stack,
are still copied to RAM. The XIP kernel is not compressed since
it has to run directly from flash, so it will take more space to
store it. The flash address used to link the kernel object files,
and for storing it, is configuration dependent. Therefore, if you
say Y here, you must know the proper physical address where to
store the kernel image depending on your own flash memory usage.
Also note that the make target becomes "make xipImage" rather than
"make zImage" or "make Image". The final kernel binary to put in
[31mCONFIG_ROM[0m memory will be arch/arm/boot/xipImage.
If unsure, say N.
config [31mCONFIG_XIP_PHYS_ADDR[0m
hex "XIP Kernel Physical Location"
depends on [31mCONFIG_XIP_KERNEL[0m
default "0x00080000"
help
This is the physical address in your flash memory the kernel will
be linked for and stored to. This address is dependent on your
own flash usage.
config [31mCONFIG_XIP_DEFLATED_DATA[0m
bool "Store kernel .data section compressed in ROM"
depends on [31mCONFIG_XIP_KERNEL[0m
select [31mCONFIG_ZLIB_INFLATE[0m
help
Before the kernel is actually executed, its .data section has to be
copied to RAM from [31mCONFIG_ROM[0m. This option allows for storing that data
in compressed form and decompressed to RAM rather than merely being
copied, saving some precious [31mCONFIG_ROM[0m space. [31mCONFIG_A[0m possible drawback is a
slightly longer boot delay.
config [31mCONFIG_KEXEC[0m
bool "Kexec system call (EXPERIMENTAL)"
depends on (![31mCONFIG_SMP[0m || [31mCONFIG_PM_SLEEP_SMP[0m)
depends on ![31mCONFIG_CPU_V7M[0m
select [31mCONFIG_KEXEC_CORE[0m
help
kexec is a system call that implements the ability to shutdown your
current kernel, and to start another kernel. It is like a reboot
but it is independent of the system firmware. And like a reboot
you can start any kernel with it, not just Linux.
It is an ongoing process to be certain the hardware in a machine
is properly shutdown, so do not be surprised if this code does not
initially work for you.
config [31mCONFIG_ATAGS_PROC[0m
bool "Export atags in procfs"
depends on [31mCONFIG_ATAGS[0m && [31mCONFIG_KEXEC[0m
default y
help
Should the atags used to boot the kernel be exported in an "atags"
file in procfs. Useful with kexec.
config [31mCONFIG_CRASH_DUMP[0m
bool "Build kdump crash kernel (EXPERIMENTAL)"
help
Generate crash dump after being started by kexec. This should
be normally only set in special crash dump kernels which are
loaded in the main kernel with kexec-tools into a specially
reserved region and then later executed after a crash by
kdump/kexec. The crash dump kernel must be compiled to a
memory address not used by the main kernel
For more details see Documentation/admin-guide/kdump/kdump.rst
config [31mCONFIG_AUTO_ZRELADDR[0m
bool "Auto calculation of the decompressed kernel image address"
help
ZRELADDR is the physical address where the decompressed kernel
image will be placed. If [31mCONFIG_AUTO_ZRELADDR[0m is selected, the address
will be determined at run-time by masking the current IP with
0xf8000000. This assumes the zImage being placed in the first 128MB
from start of memory.
config [31mCONFIG_EFI_STUB[0m
bool
config [31mCONFIG_EFI[0m
bool "UEFI runtime support"
depends on [31mCONFIG_OF[0m && ![31mCONFIG_CPU_BIG_ENDIAN[0m && [31mCONFIG_MMU[0m && [31mCONFIG_AUTO_ZRELADDR[0m && ![31mCONFIG_XIP_KERNEL[0m
select [31mCONFIG_UCS2_STRING[0m
select [31mCONFIG_EFI_PARAMS_FROM_FDT[0m
select [31mCONFIG_EFI_STUB[0m
select [31mCONFIG_EFI_ARMSTUB[0m
select [31mCONFIG_EFI_RUNTIME_WRAPPERS[0m
---help---
This option provides support for runtime services provided
by UEFI firmware (such as non-volatile variables, realtime
clock, and platform reset). [31mCONFIG_A[0m UEFI stub is also provided to
allow the kernel to be booted as an [31mCONFIG_EFI[0m application. This
is only useful for kernels that may run on systems that have
UEFI firmware.
config [31mCONFIG_DMI[0m
bool "Enable support for SMBIOS (DMI) tables"
depends on [31mCONFIG_EFI[0m
default y
help
This enables SMBIOS/[31mCONFIG_DMI[0m feature for systems.
This option is only useful on systems that have UEFI firmware.
However, even with this option, the resultant kernel should
continue to boot on existing non-UEFI platforms.
NOTE: This does *NOT* enable or encourage the use of [31mCONFIG_DMI[0m quirks,
i.e., the the practice of identifying the platform via [31mCONFIG_DMI[0m to
decide whether certain workarounds for buggy hardware and/or
firmware need to be enabled. This would require the [31mCONFIG_DMI[0m subsystem
to be enabled much earlier than we do on [31mCONFIG_ARM[0m, which is non-trivial.
endmenu
menu "CPU Power Management"
source "drivers/cpufreq/Kconfig"
source "drivers/cpuidle/Kconfig"
endmenu
menu "Floating point emulation"
comment "At least one emulation must be selected"
config [31mCONFIG_FPE_NWFPE[0m
bool "NWFPE math emulation"
depends on (![31mCONFIG_AEABI[0m || [31mCONFIG_OABI_COMPAT[0m) && ![31mCONFIG_THUMB2_KERNEL[0m
---help---
Say Y to include the NWFPE floating point emulator in the kernel.
This is necessary to run most binaries. Linux does not currently
support floating point hardware so you need to say Y here even if
your machine has an FPA or floating point co-processor podule.
You may say N here if you are going to load the Acorn FPEmulator
early in the bootup.
config [31mCONFIG_FPE_NWFPE_XP[0m
bool "Support extended precision"
depends on [31mCONFIG_FPE_NWFPE[0m
help
Say Y to include 80-bit support in the kernel floating-point
emulator. Otherwise, only 32 and 64-bit support is compiled in.
Note that gcc does not generate 80-bit operations by default,
so in most cases this option only enlarges the size of the
floating point emulator without any good reason.
You almost surely want to say N here.
config [31mCONFIG_FPE_FASTFPE[0m
bool "FastFPE math emulation (EXPERIMENTAL)"
depends on (![31mCONFIG_AEABI[0m || [31mCONFIG_OABI_COMPAT[0m) && ![31mCONFIG_CPU_32v3[0m
---help---
Say Y here to include the FAST floating point emulator in the kernel.
This is an experimental much faster emulator which now also has full
precision for the mantissa. It does not support any exceptions.
It is very simple, and approximately 3-6 times faster than NWFPE.
It should be sufficient for most programs. It may be not suitable
for scientific calculations, but you have to check this for yourself.
If you do not feel you need a faster FP emulation you should better
choose NWFPE.
config [31mCONFIG_VFP[0m
bool "VFP-format floating point maths"
depends on [31mCONFIG_CPU_V6[0m || [31mCONFIG_CPU_V6K[0m || [31mCONFIG_CPU_ARM926T[0m || [31mCONFIG_CPU_V7[0m || [31mCONFIG_CPU_FEROCEON[0m
help
Say Y to include [31mCONFIG_VFP[0m support code in the kernel. This is needed
if your hardware includes a [31mCONFIG_VFP[0m unit.
Please see <file:Documentation/arm/vfp/release-notes.rst> for
release notes and additional status information.
Say N if your target does not have [31mCONFIG_VFP[0m hardware.
config [31mCONFIG_VFPv3[0m
bool
depends on [31mCONFIG_VFP[0m
default y if [31mCONFIG_CPU_V7[0m
config [31mCONFIG_NEON[0m
bool "Advanced SIMD (NEON) Extension support"
depends on [31mCONFIG_VFPv3[0m && [31mCONFIG_CPU_V7[0m
help
Say Y to include support code for [31mCONFIG_NEON[0m, the ARMv7 Advanced SIMD
Extension.
config [31mCONFIG_KERNEL_MODE_NEON[0m
bool "Support for NEON in kernel mode"
depends on [31mCONFIG_NEON[0m && [31mCONFIG_AEABI[0m
help
Say Y to include support for [31mCONFIG_NEON[0m in kernel mode.
endmenu
menu "Power management options"
source "kernel/power/Kconfig"
config [31mCONFIG_ARCH_SUSPEND_POSSIBLE[0m
depends on [31mCONFIG_CPU_ARM920T[0m || [31mCONFIG_CPU_ARM926T[0m || [31mCONFIG_CPU_FEROCEON[0m || [31mCONFIG_CPU_SA1100[0m || \
[31mCONFIG_CPU_V6[0m || [31mCONFIG_CPU_V6K[0m || [31mCONFIG_CPU_V7[0m || [31mCONFIG_CPU_V7M[0m || [31mCONFIG_CPU_XSC3[0m || [31mCONFIG_CPU_XSCALE[0m || [31mCONFIG_CPU_MOHAWK[0m
def_bool y
config [31mCONFIG_ARM_CPU_SUSPEND[0m
def_bool [31mCONFIG_PM_SLEEP[0m || [31mCONFIG_BL_SWITCHER[0m || [31mCONFIG_ARM_PSCI_FW[0m
depends on [31mCONFIG_ARCH_SUSPEND_POSSIBLE[0m
config [31mCONFIG_ARCH_HIBERNATION_POSSIBLE[0m
bool
depends on [31mCONFIG_MMU[0m
default y if [31mCONFIG_ARCH_SUSPEND_POSSIBLE[0m
endmenu
source "drivers/firmware/Kconfig"
if [31mCONFIG_CRYPTO[0m
source "arch/arm/crypto/Kconfig"
endif
source "arch/arm/kvm/Kconfig"