# SPDX-License-Identifier: GPL-2.0-only
menuconfig [31mCONFIG_ARCH_AT91[0m
bool "AT91/Microchip SoCs"
depends on [31mCONFIG_ARCH_MULTI_V4T[0m || [31mCONFIG_ARCH_MULTI_V5[0m || [31mCONFIG_ARCH_MULTI_V7[0m || [31mCONFIG_ARM_SINGLE_ARMV7M[0m
select [31mCONFIG_ARM_CPU_SUSPEND[0m if [31mCONFIG_PM[0m && [31mCONFIG_ARCH_MULTI_V7[0m
select [31mCONFIG_COMMON_CLK_AT91[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_PINCTRL[0m
select [31mCONFIG_SOC_BUS[0m
if [31mCONFIG_ARCH_AT91[0m
config [31mCONFIG_SOC_SAMV7[0m
bool "SAM Cortex-M7 family" if [31mCONFIG_ARM_SINGLE_ARMV7M[0m
select [31mCONFIG_COMMON_CLK_AT91[0m
select [31mCONFIG_PINCTRL_AT91[0m
help
Select this if you are using an SoC from Microchip's SAME7, SAMS7 or SAMV7
families.
config [31mCONFIG_SOC_SAMA5D2[0m
bool "SAMA5D2 family"
depends on [31mCONFIG_ARCH_MULTI_V7[0m
select [31mCONFIG_SOC_SAMA5[0m
select [31mCONFIG_CACHE_L2X0[0m
select [31mCONFIG_HAVE_AT91_UTMI[0m
select [31mCONFIG_HAVE_AT91_USB_CLK[0m
select [31mCONFIG_HAVE_AT91_H32MX[0m
select [31mCONFIG_HAVE_AT91_GENERATED_CLK[0m
select [31mCONFIG_HAVE_AT91_AUDIO_PLL[0m
select [31mCONFIG_HAVE_AT91_I2S_MUX_CLK[0m
select [31mCONFIG_PINCTRL_AT91PIO4[0m
help
Select this if ou are using one of Microchip's SAMA5D2 family SoC.
config [31mCONFIG_SOC_SAMA5D3[0m
bool "SAMA5D3 family"
depends on [31mCONFIG_ARCH_MULTI_V7[0m
select [31mCONFIG_SOC_SAMA5[0m
select [31mCONFIG_HAVE_AT91_UTMI[0m
select [31mCONFIG_HAVE_AT91_SMD[0m
select [31mCONFIG_HAVE_AT91_USB_CLK[0m
select [31mCONFIG_PINCTRL_AT91[0m
help
Select this if you are using one of Microchip's SAMA5D3 family SoC.
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
config [31mCONFIG_SOC_SAMA5D4[0m
bool "SAMA5D4 family"
depends on [31mCONFIG_ARCH_MULTI_V7[0m
select [31mCONFIG_SOC_SAMA5[0m
select [31mCONFIG_CACHE_L2X0[0m
select [31mCONFIG_HAVE_AT91_UTMI[0m
select [31mCONFIG_HAVE_AT91_SMD[0m
select [31mCONFIG_HAVE_AT91_USB_CLK[0m
select [31mCONFIG_HAVE_AT91_H32MX[0m
select [31mCONFIG_PINCTRL_AT91[0m
help
Select this if you are using one of Microchip's SAMA5D4 family SoC.
config [31mCONFIG_SOC_AT91RM9200[0m
bool "AT91RM9200"
depends on [31mCONFIG_ARCH_MULTI_V4T[0m
select [31mCONFIG_ATMEL_AIC_IRQ[0m
select [31mCONFIG_ATMEL_PM[0m if [31mCONFIG_PM[0m
select [31mCONFIG_ATMEL_ST[0m
select [31mCONFIG_CPU_ARM920T[0m
select [31mCONFIG_HAVE_AT91_USB_CLK[0m
select [31mCONFIG_PINCTRL_AT91[0m
select [31mCONFIG_SOC_SAM_V4_V5[0m
select [31mCONFIG_SRAM[0m if [31mCONFIG_PM[0m
help
Select this if you are using Microchip's AT91RM9200 SoC.
config [31mCONFIG_SOC_AT91SAM9[0m
bool "AT91SAM9"
depends on [31mCONFIG_ARCH_MULTI_V5[0m
select [31mCONFIG_ATMEL_AIC_IRQ[0m
select [31mCONFIG_ATMEL_PM[0m if [31mCONFIG_PM[0m
select [31mCONFIG_ATMEL_SDRAMC[0m
select [31mCONFIG_CPU_ARM926T[0m
select [31mCONFIG_HAVE_AT91_SMD[0m
select [31mCONFIG_HAVE_AT91_USB_CLK[0m
select [31mCONFIG_HAVE_AT91_UTMI[0m
select [31mCONFIG_HAVE_FB_ATMEL[0m
select [31mCONFIG_MEMORY[0m
select [31mCONFIG_PINCTRL_AT91[0m
select [31mCONFIG_SOC_SAM_V4_V5[0m
select [31mCONFIG_SRAM[0m if [31mCONFIG_PM[0m
help
Select this if you are using one of those Microchip SoC:
AT91SAM9260
AT91SAM9261
AT91SAM9263
AT91SAM9G15
AT91SAM9G20
AT91SAM9G25
AT91SAM9G35
AT91SAM9G45
AT91SAM9G46
AT91SAM9M10
AT91SAM9M11
AT91SAM9N12
AT91SAM9RL
AT91SAM9X25
AT91SAM9X35
AT91SAM9XE
comment "Clocksource driver selection"
config [31mCONFIG_ATMEL_CLOCKSOURCE_PIT[0m
bool "Periodic Interval Timer (PIT) support"
depends on [31mCONFIG_SOC_AT91SAM9[0m || [31mCONFIG_SOC_SAMA5[0m
default [31mCONFIG_SOC_AT91SAM9[0m || [31mCONFIG_SOC_SAMA5[0m
select [31mCONFIG_ATMEL_PIT[0m
help
Select this to get a clocksource based on the Atmel Periodic Interval
Timer. It has a relatively low resolution and the [31mCONFIG_TC[0m Block clocksource
should be preferred.
config [31mCONFIG_ATMEL_CLOCKSOURCE_TCB[0m
bool "Timer Counter Blocks (TCB) support"
default [31mCONFIG_SOC_AT91RM9200[0m || [31mCONFIG_SOC_AT91SAM9[0m || [31mCONFIG_SOC_SAMA5[0m
select [31mCONFIG_ATMEL_TCB_CLKSRC[0m
help
Select this to get a high precision clocksource based on a
[31mCONFIG_TC[0m block with a 5+ MHz base clock rate.
On platforms with 16-bit counters, two timer channels are combined
to make a single 32-bit timer.
It can also be used as a clock event device supporting oneshot mode.
config [31mCONFIG_HAVE_AT91_UTMI[0m
bool
config [31mCONFIG_HAVE_AT91_USB_CLK[0m
bool
config [31mCONFIG_COMMON_CLK_AT91[0m
bool
select [31mCONFIG_COMMON_CLK[0m
select [31mCONFIG_MFD_SYSCON[0m
config [31mCONFIG_HAVE_AT91_SMD[0m
bool
config [31mCONFIG_HAVE_AT91_H32MX[0m
bool
config [31mCONFIG_HAVE_AT91_GENERATED_CLK[0m
bool
config [31mCONFIG_HAVE_AT91_AUDIO_PLL[0m
bool
config [31mCONFIG_HAVE_AT91_I2S_MUX_CLK[0m
bool
config [31mCONFIG_SOC_SAM_V4_V5[0m
bool
config [31mCONFIG_SOC_SAM_V7[0m
bool
config [31mCONFIG_SOC_SAMA5[0m
bool
select [31mCONFIG_ATMEL_AIC5_IRQ[0m
select [31mCONFIG_ATMEL_PM[0m if [31mCONFIG_PM[0m
select [31mCONFIG_ATMEL_SDRAMC[0m
select [31mCONFIG_MEMORY[0m
select [31mCONFIG_SOC_SAM_V7[0m
select [31mCONFIG_SRAM[0m if [31mCONFIG_PM[0m
config [31mCONFIG_ATMEL_PM[0m
bool
endif