# SPDX-License-Identifier: GPL-2.0
menu "Platform support"
source "arch/powerpc/platforms/powernv/Kconfig"
source "arch/powerpc/platforms/pseries/Kconfig"
source "arch/powerpc/platforms/chrp/Kconfig"
source "arch/powerpc/platforms/512x/Kconfig"
source "arch/powerpc/platforms/52xx/Kconfig"
source "arch/powerpc/platforms/powermac/Kconfig"
source "arch/powerpc/platforms/maple/Kconfig"
source "arch/powerpc/platforms/pasemi/Kconfig"
source "arch/powerpc/platforms/ps3/Kconfig"
source "arch/powerpc/platforms/cell/Kconfig"
source "arch/powerpc/platforms/8xx/Kconfig"
source "arch/powerpc/platforms/82xx/Kconfig"
source "arch/powerpc/platforms/83xx/Kconfig"
source "arch/powerpc/platforms/85xx/Kconfig"
source "arch/powerpc/platforms/86xx/Kconfig"
source "arch/powerpc/platforms/embedded6xx/Kconfig"
source "arch/powerpc/platforms/44x/Kconfig"
source "arch/powerpc/platforms/40x/Kconfig"
source "arch/powerpc/platforms/amigaone/Kconfig"
config [31mCONFIG_KVM_GUEST[0m
bool "KVM Guest support"
select [31mCONFIG_EPAPR_PARAVIRT[0m
---help---
This option enables various optimizations for running under the [31mCONFIG_KVM[0m
hypervisor. Overhead for the kernel when not running inside [31mCONFIG_KVM[0m should
be minimal.
In case of doubt, say Y
config [31mCONFIG_EPAPR_PARAVIRT[0m
bool "ePAPR para-virtualization support"
help
Enables ePAPR para-virtualization support for guests.
In case of doubt, say Y
config [31mCONFIG_PPC_NATIVE[0m
bool
depends on [31mCONFIG_PPC_BOOK3S_32[0m || [31mCONFIG_PPC64[0m
help
Support for running natively on the hardware, i.e. without
a hypervisor. This option is not user-selectable but should
be selected by all platforms that need it.
config [31mCONFIG_PPC_OF_BOOT_TRAMPOLINE[0m
bool "Support booting from Open Firmware or yaboot"
depends on [31mCONFIG_PPC_BOOK3S_32[0m || [31mCONFIG_PPC64[0m
default y
help
Support from booting from Open Firmware or yaboot using an
Open Firmware client interface. This enables the kernel to
communicate with open firmware to retrieve system information
such as the device tree.
In case of doubt, say Y
config [31mCONFIG_PPC_DT_CPU_FTRS[0m
bool "Device-tree based CPU feature discovery & setup"
depends on [31mCONFIG_PPC_BOOK3S_64[0m
default y
help
This enables code to use a new device tree binding for describing CPU
compatibility and features. Saying Y here will attempt to use the new
binding if the firmware provides it. Currently only the skiboot
firmware provides this binding.
If you're not sure say Y.
config [31mCONFIG_UDBG_RTAS_CONSOLE[0m
bool "RTAS based debug console"
depends on [31mCONFIG_PPC_RTAS[0m
config [31mCONFIG_PPC_SMP_MUXED_IPI[0m
bool
help
Select this option if your platform supports [31mCONFIG_SMP[0m and your
interrupt controller provides less than 4 interrupts to each
cpu. This will enable the generic code to multiplex the 4
messages on to one ipi.
config [31mCONFIG_IPIC[0m
bool
config [31mCONFIG_MPIC[0m
bool
config [31mCONFIG_MPIC_TIMER[0m
bool "MPIC Global Timer"
depends on [31mCONFIG_MPIC[0m && [31mCONFIG_FSL_SOC[0m
help
The [31mCONFIG_MPIC[0m global timer is a hardware timer inside the
Freescale PIC complying with OpenPIC standard. When the
specified interval times out, the hardware timer generates
an interrupt. The driver currently is only tested on fsl
chip, but it can potentially support other global timers
complying with the OpenPIC standard.
config [31mCONFIG_FSL_MPIC_TIMER_WAKEUP[0m
tristate "Freescale MPIC global timer wakeup driver"
depends on [31mCONFIG_FSL_SOC[0m && [31mCONFIG_MPIC_TIMER[0m && [31mCONFIG_PM[0m
help
The driver provides a way to wake up the system by [31mCONFIG_MPIC[0m
timer.
e.g. "echo 5 > /sys/devices/system/mpic/timer_wakeup"
config [31mCONFIG_PPC_EPAPR_HV_PIC[0m
bool
select [31mCONFIG_EPAPR_PARAVIRT[0m
config [31mCONFIG_MPIC_WEIRD[0m
bool
config [31mCONFIG_MPIC_MSGR[0m
bool "MPIC message register support"
depends on [31mCONFIG_MPIC[0m
help
Enables support for the [31mCONFIG_MPIC[0m message registers. These
registers are used for inter-processor communication.
config [31mCONFIG_PPC_I8259[0m
bool
config [31mCONFIG_U3_DART[0m
bool
depends on [31mCONFIG_PPC64[0m
config [31mCONFIG_PPC_RTAS[0m
bool
config [31mCONFIG_RTAS_ERROR_LOGGING[0m
bool
depends on [31mCONFIG_PPC_RTAS[0m
config [31mCONFIG_PPC_RTAS_DAEMON[0m
bool
depends on [31mCONFIG_PPC_RTAS[0m
config [31mCONFIG_RTAS_PROC[0m
bool "Proc interface to RTAS"
depends on [31mCONFIG_PPC_RTAS[0m && [31mCONFIG_PROC_FS[0m
default y
config [31mCONFIG_RTAS_FLASH[0m
tristate "Firmware flash interface"
depends on [31mCONFIG_PPC64[0m && [31mCONFIG_RTAS_PROC[0m
config [31mCONFIG_MMIO_NVRAM[0m
bool
config [31mCONFIG_MPIC_U3_HT_IRQS[0m
bool
config [31mCONFIG_MPIC_BROKEN_REGREAD[0m
bool
depends on [31mCONFIG_MPIC[0m
help
This option enables a [31mCONFIG_MPIC[0m driver workaround for some chips
that have a bug that causes some interrupt source information
to not read back properly. It is safe to use on other chips as
well, but enabling it uses about 8KB of memory to keep copies
of the register contents in software.
config [31mCONFIG_EEH[0m
bool
depends on ([31mCONFIG_PPC_POWERNV[0m || [31mCONFIG_PPC_PSERIES[0m) && [31mCONFIG_PCI[0m
default y
config [31mCONFIG_PPC_MPC106[0m
bool
config [31mCONFIG_PPC_970_NAP[0m
bool
config [31mCONFIG_PPC_P7_NAP[0m
bool
config [31mCONFIG_PPC_INDIRECT_PIO[0m
bool
select [31mCONFIG_GENERIC_IOMAP[0m
config [31mCONFIG_PPC_INDIRECT_MMIO[0m
bool
config [31mCONFIG_PPC_IO_WORKAROUNDS[0m
bool
source "drivers/cpufreq/Kconfig"
menu "CPUIdle driver"
source "drivers/cpuidle/Kconfig"
endmenu
config [31mCONFIG_PPC601_SYNC_FIX[0m
bool "Workarounds for PPC601 bugs"
depends on [31mCONFIG_PPC_BOOK3S_601[0m && [31mCONFIG_PPC_PMAC[0m
default y
help
Some versions of the PPC601 (the first PowerPC chip) have bugs which
mean that extra synchronization instructions are required near
certain instructions, typically those that make major changes to the
CPU state. These extra instructions reduce performance slightly.
If you say N here, these extra instructions will not be included,
resulting in a kernel which will run faster but may not run at all
on some systems with the PPC601 chip.
If in doubt, say Y here.
config [31mCONFIG_TAU[0m
bool "On-chip CPU temperature sensor support"
depends on [31mCONFIG_PPC_BOOK3S_32[0m
help
G3 and G4 processors have an on-chip temperature sensor called the
'Thermal Assist Unit ([31mCONFIG_TAU[0m)', which, in theory, can measure the on-die
temperature within 2-4 degrees Celsius. This option shows the current
on-die temperature in /proc/cpuinfo if the cpu supports it.
Unfortunately, on some chip revisions, this sensor is very inaccurate
and in many cases, does not work at all, so don't assume the cpu
temp is actually what /proc/cpuinfo says it is.
config [31mCONFIG_TAU_INT[0m
bool "Interrupt driven TAU driver (DANGEROUS)"
depends on [31mCONFIG_TAU[0m
---help---
The [31mCONFIG_TAU[0m supports an interrupt driven mode which causes an interrupt
whenever the temperature goes out of range. This is the fastest way
to get notified the temp has exceeded a range. With this option off,
a timer is used to re-check the temperature periodically.
However, on some cpus it appears that the [31mCONFIG_TAU[0m interrupt hardware
is buggy and can cause a situation which would lead unexplained hard
lockups.
Unless you are extending the [31mCONFIG_TAU[0m driver, or enjoy kernel/hardware
debugging, leave this option off.
config [31mCONFIG_TAU_AVERAGE[0m
bool "Average high and low temp"
depends on [31mCONFIG_TAU[0m
---help---
The [31mCONFIG_TAU[0m hardware can compare the temperature to an upper and lower
bound. The default behavior is to show both the upper and lower
bound in /proc/cpuinfo. If the range is large, the temperature is
either changing a lot, or the [31mCONFIG_TAU[0m hardware is broken (likely on some
G4's). If the range is small (around 4 degrees), the temperature is
relatively stable. If you say Y here, a single temperature value,
halfway between the upper and lower bounds, will be reported in
/proc/cpuinfo.
If in doubt, say N here.
config [31mCONFIG_QE_GPIO[0m
bool "QE GPIO support"
depends on [31mCONFIG_QUICC_ENGINE[0m
select [31mCONFIG_GPIOLIB[0m
help
Say Y here if you're going to use hardware that connects to the
QE GPIOs.
config [31mCONFIG_CPM2[0m
bool "Enable support for the CPM2 (Communications Processor Module)"
depends on ([31mCONFIG_FSL_SOC_BOOKE[0m && [31mCONFIG_PPC32[0m) || [31mCONFIG_8260[0m
select [31mCONFIG_CPM[0m
select [31mCONFIG_HAVE_PCI[0m
select [31mCONFIG_GPIOLIB[0m
help
The [31mCONFIG_CPM2[0m (Communications Processor Module) is a coprocessor on
embedded CPUs made by Freescale. Selecting this option means that
you wish to build a kernel for a machine with a [31mCONFIG_CPM2[0m coprocessor
on it (826x, 827x, 8560).
config [31mCONFIG_FSL_ULI1575[0m
bool
select [31mCONFIG_GENERIC_ISA_DMA[0m
help
Supports for the ULI1575 PCIe south bridge that exists on some
Freescale reference boards. The boards all use the ULI in pretty
much the same way.
config [31mCONFIG_CPM[0m
bool
select [31mCONFIG_GENERIC_ALLOCATOR[0m
config [31mCONFIG_OF_RTC[0m
bool
help
Uses information from the [31mCONFIG_OF[0m or flattened device tree to instantiate
platform devices for direct mapped [31mCONFIG_RTC[0m chips like the DS1742 or DS1743.
config [31mCONFIG_GEN_RTC[0m
bool "Use the platform RTC operations from user space"
select [31mCONFIG_RTC_CLASS[0m
select [31mCONFIG_RTC_DRV_GENERIC[0m
help
This option provides backwards compatibility with the old gen_rtc.ko
module that was traditionally used for old PowerPC machines.
Platforms should migrate to enabling the [31mCONFIG_RTC_DRV_GENERIC[0m by hand
replacing their get_rtc_time/set_rtc_time callbacks with
a proper [31mCONFIG_RTC[0m device driver.
config [31mCONFIG_SIMPLE_GPIO[0m
bool "Support for simple, memory-mapped GPIO controllers"
depends on [31mCONFIG_PPC[0m
select [31mCONFIG_GPIOLIB[0m
help
Say Y here to support simple, memory-mapped GPIO controllers.
These are usually BCSRs used to control board's switches, LEDs,
chip-selects, Ethernet/[31mCONFIG_USB[0m PHY's power and various other small
on-board peripherals.
config [31mCONFIG_MCU_MPC8349EMITX[0m
bool "MPC8349E-mITX MCU driver"
depends on [31mCONFIG_I2C[0m=y && [31mCONFIG_PPC_83xx[0m
select [31mCONFIG_GPIOLIB[0m
help
Say Y here to enable soft power-off functionality on the Freescale
boards with the MPC8349E-mITX-compatible MCU chips. This driver will
also register MCU GPIOs with the generic GPIO API, so you'll able
to use MCU pins as GPIOs.
config [31mCONFIG_XILINX_PCI[0m
bool "Xilinx PCI host bridge support"
depends on [31mCONFIG_PCI[0m && [31mCONFIG_XILINX_VIRTEX[0m
endmenu