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Open Menu /tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json 
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[
    {
        "PEBS": "1",
        "PublicDescription": "This event counts the number of load ops retired that had DTLB miss.",
        "EventCode": "0x04",
        "Counter": "0,1",
        "UMask": "0x8",
        "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
        "SampleAfterValue": "200003",
        "BriefDescription": "Loads missed DTLB"
    },
    {
        "PublicDescription": "This event counts when a data (D) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
        "EventCode": "0x05",
        "Counter": "0,1",
        "UMask": "0x1",
        "EventName": "PAGE_WALKS.D_SIDE_WALKS",
        "SampleAfterValue": "100003",
        "BriefDescription": "D-side page-walks",
        "EdgeDetect": "1"
    },
    {
        "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
        "EventCode": "0x05",
        "Counter": "0,1",
        "UMask": "0x1",
        "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
        "SampleAfterValue": "200003",
        "BriefDescription": "Duration of D-side page-walks in core cycles"
    },
    {
        "PublicDescription": "This event counts when an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
        "EventCode": "0x05",
        "Counter": "0,1",
        "UMask": "0x2",
        "EventName": "PAGE_WALKS.I_SIDE_WALKS",
        "SampleAfterValue": "100003",
        "BriefDescription": "I-side page-walks",
        "EdgeDetect": "1"
    },
    {
        "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
        "EventCode": "0x05",
        "Counter": "0,1",
        "UMask": "0x2",
        "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
        "SampleAfterValue": "200003",
        "BriefDescription": "Duration of I-side page-walks in core cycles"
    },
    {
        "PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
        "EventCode": "0x05",
        "Counter": "0,1",
        "UMask": "0x3",
        "EventName": "PAGE_WALKS.WALKS",
        "SampleAfterValue": "100003",
        "BriefDescription": "Total page walks that are completed (I-side and D-side)",
        "EdgeDetect": "1"
    },
    {
        "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.  Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.",
        "EventCode": "0x05",
        "Counter": "0,1",
        "UMask": "0x3",
        "EventName": "PAGE_WALKS.CYCLES",
        "SampleAfterValue": "200003",
        "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)"
    }
]