Training courses

Kernel and Embedded Linux

Bootlin training courses

Embedded Linux, kernel,
Yocto Project, Buildroot, real-time,
graphics, boot time, debugging...

Bootlin logo

Elixir Cross Referencer

Open Menu /Documentation/devicetree/bindings/i2c/i2c-stm32.txt 
 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
* I2C controller embedded in STMicroelectronics STM32 I2C platform

Required properties:
- compatible: Must be one of the following
  - "st,stm32f4-i2c"
  - "st,stm32f7-i2c"
- reg: Offset and length of the register set for the device
- interrupts: Must contain the interrupt id for I2C event and then the
  interrupt id for I2C error.
- resets: Must contain the phandle to the reset controller.
- clocks: Must contain the input clock of the I2C instance.
- A pinctrl state named "default" must be defined to set pins in mode of
  operation for I2C transfer
- #address-cells = <1>;
- #size-cells = <0>;

Optional properties:
- clock-frequency: Desired I2C bus clock frequency in Hz. If not specified,
  the default 100 kHz frequency will be used.
  For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are
  100000 and 400000.
  For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode, Fast-mode and Fast-mode
  Plus are supported, possible values are 100000, 400000 and 1000000.
- dmas: List of phandles to rx and tx DMA channels. Refer to stm32-dma.txt.
- dma-names: List of dma names. Valid names are: "rx" and "tx".
- i2c-scl-rising-time-ns: I2C SCL Rising time for the board (default: 25)
  For STM32F7, STM32H7 and STM32MP1 only.
- i2c-scl-falling-time-ns: I2C SCL Falling time for the board (default: 10)
  For STM32F7, STM32H7 and STM32MP1 only.
  I2C Timings are derived from these 2 values
- st,syscfg-fmp: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode
  Plus speed is selected by slave.
	1st cell: phandle to syscfg
	2nd cell: register offset within SYSCFG
	3rd cell: register bitmask for FMP bit
  For STM32F7, STM32H7 and STM32MP1 only.

Example:

	i2c@40005400 {
		compatible = "st,stm32f4-i2c";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x40005400 0x400>;
		interrupts = <31>,
			     <32>;
		resets = <&rcc 277>;
		clocks = <&rcc 0 149>;
		pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
		pinctrl-names = "default";
	};

	i2c@40005400 {
		compatible = "st,stm32f7-i2c";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x40005400 0x400>;
		interrupts = <31>,
			     <32>;
		resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
		clocks = <&rcc 1 CLK_I2C1>;
		pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
		pinctrl-names = "default";
		st,syscfg-fmp = <&syscfg 0x4 0x1>;
	};