Analog Devices ADIS16480 and similar IMUs

Required properties for the ADIS16480:

- compatible: Must be one of
	* "adi,adis16375"
	* "adi,adis16480"
	* "adi,adis16485"
	* "adi,adis16488"
	* "adi,adis16495-1"
	* "adi,adis16495-2"
	* "adi,adis16495-3"
	* "adi,adis16497-1"
	* "adi,adis16497-2"
	* "adi,adis16497-3"
- reg: SPI chip select number for the device
- spi-max-frequency: Max SPI frequency to use
	see: Documentation/devicetree/bindings/spi/spi-bus.txt
- spi-cpha: See Documentation/devicetree/bindings/spi/spi-bus.txt
- spi-cpol: See Documentation/devicetree/bindings/spi/spi-bus.txt
- interrupts: interrupt mapping for IRQ, accepted values are:
	* IRQF_TRIGGER_RISING
	* IRQF_TRIGGER_FALLING

Optional properties:

- interrupt-names: Data ready line selection. Valid values are:
	* DIO1
	* DIO2
	* DIO3
	* DIO4
	If this field is left empty, DIO1 is assigned as default data ready
	signal.
- reset-gpios: must be the device tree identifier of the RESET pin. As the line
	is active low, it should be marked GPIO_ACTIVE_LOW.
- clocks: phandle to the external clock. Should be set according to
	"clock-names".
	If this field is left empty together with the "clock-names" field, then
	the internal clock is used.
- clock-names: The name of the external clock to be used. Valid values are:
	* sync: In sync mode, the internal clock is disabled and the frequency
		of the external clock signal establishes therate of data
		collection and processing. See Fig 14 and 15 in the datasheet.
		The clock-frequency must be:
		* 3000 to 4500 Hz for adis1649x devices.
		* 700 to 2400 Hz for adis1648x devices.
	* pps: In Pulse Per Second (PPS) Mode, the rate of data collection and
	       production is equal to the product of the external clock
	       frequency and the scale factor in the SYNC_SCALE register, see
	       Table 154 in the datasheet.
	       The clock-frequency must be:
	       * 1 to 128 Hz for adis1649x devices.
	       * This mode is not supported by adis1648x devices.
	If this field is left empty together with the "clocks" field, then the
	internal clock is used.
- adi,ext-clk-pin: The DIOx line to be used as an external clock input.
	Valid values are:
	* DIO1
	* DIO2
	* DIO3
	* DIO4
	Each DIOx pin supports only one function at a time (data ready line
	selection or external clock input). When a single pin has two
	two assignments, the enable bit for the lower priority function
	automatically resets to zero (disabling the lower priority function).
	Data ready has highest priority.
	If this field is left empty, DIO2 is assigned as default external clock
	input pin.

Example:

	imu@0 {
		compatible = "adi,adis16495-1";
		reg = <0>;
		spi-max-frequency = <3200000>;
		spi-cpol;
		spi-cpha;
		interrupts = <25 IRQF_TRIGGER_FALLING>;
		interrupt-parent = <&gpio>;
		interrupt-names = "DIO2";
		clocks = <&adis16495_sync>;
		clock-names = "sync";
		adi,ext-clk-pin = "DIO1";
	};