# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright ([31mCONFIG_C[0m) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
#
config [31mCONFIG_ARC[0m
def_bool y
select [31mCONFIG_ARC_TIMERS[0m
select [31mCONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN[0m
select [31mCONFIG_ARCH_HAS_DMA_PREP_COHERENT[0m
select [31mCONFIG_ARCH_HAS_PTE_SPECIAL[0m
select [31mCONFIG_ARCH_HAS_SETUP_DMA_OPS[0m
select [31mCONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU[0m
select [31mCONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE[0m
select [31mCONFIG_ARCH_SUPPORTS_ATOMIC_RMW[0m if [31mCONFIG_ARC_HAS_LLSC[0m
select [31mCONFIG_ARCH_32BIT_OFF_T[0m
select [31mCONFIG_BUILDTIME_EXTABLE_SORT[0m
select [31mCONFIG_CLONE_BACKWARDS[0m
select [31mCONFIG_COMMON_CLK[0m
select [31mCONFIG_DMA_DIRECT_REMAP[0m
select [31mCONFIG_GENERIC_ATOMIC64[0m if ![31mCONFIG_ISA_ARCV2[0m || !([31mCONFIG_ARC_HAS_LL64[0m && [31mCONFIG_ARC_HAS_LLSC[0m)
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_GENERIC_FIND_FIRST_BIT[0m
# for now, we don't need [31mCONFIG_GENERIC_IRQ_PROBE[0m, CONFIG_GENERIC_IRQ_CHIP
select [31mCONFIG_GENERIC_IRQ_SHOW[0m
select [31mCONFIG_GENERIC_PCI_IOMAP[0m
select [31mCONFIG_GENERIC_PENDING_IRQ[0m if [31mCONFIG_SMP[0m
select [31mCONFIG_GENERIC_SCHED_CLOCK[0m
select [31mCONFIG_GENERIC_SMP_IDLE_THREAD[0m
select [31mCONFIG_HAVE_ARCH_KGDB[0m
select [31mCONFIG_HAVE_ARCH_TRACEHOOK[0m
select [31mCONFIG_HAVE_DEBUG_STACKOVERFLOW[0m
select [31mCONFIG_HAVE_FUTEX_CMPXCHG[0m if [31mCONFIG_FUTEX[0m
select [31mCONFIG_HAVE_IOREMAP_PROT[0m
select [31mCONFIG_HAVE_KERNEL_GZIP[0m
select [31mCONFIG_HAVE_KERNEL_LZMA[0m
select [31mCONFIG_HAVE_KPROBES[0m
select [31mCONFIG_HAVE_KRETPROBES[0m
select [31mCONFIG_HAVE_MOD_ARCH_SPECIFIC[0m
select [31mCONFIG_HAVE_OPROFILE[0m
select [31mCONFIG_HAVE_PERF_EVENTS[0m
select [31mCONFIG_HANDLE_DOMAIN_IRQ[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_MODULES_USE_ELF_RELA[0m
select [31mCONFIG_OF[0m
select [31mCONFIG_OF_EARLY_FLATTREE[0m
select [31mCONFIG_PCI_SYSCALL[0m if [31mCONFIG_PCI[0m
select [31mCONFIG_PERF_USE_VMALLOC[0m if [31mCONFIG_ARC_CACHE_VIPT_ALIASING[0m
config [31mCONFIG_ARCH_HAS_CACHE_LINE_SIZE[0m
def_bool y
config [31mCONFIG_TRACE_IRQFLAGS_SUPPORT[0m
def_bool y
config [31mCONFIG_LOCKDEP_SUPPORT[0m
def_bool y
config [31mCONFIG_SCHED_OMIT_FRAME_POINTER[0m
def_bool y
config [31mCONFIG_GENERIC_CSUM[0m
def_bool y
config [31mCONFIG_ARCH_DISCONTIGMEM_ENABLE[0m
def_bool n
config [31mCONFIG_ARCH_FLATMEM_ENABLE[0m
def_bool y
config [31mCONFIG_MMU[0m
def_bool y
config [31mCONFIG_NO_IOPORT_MAP[0m
def_bool y
config [31mCONFIG_GENERIC_CALIBRATE_DELAY[0m
def_bool y
config [31mCONFIG_GENERIC_HWEIGHT[0m
def_bool y
config [31mCONFIG_STACKTRACE_SUPPORT[0m
def_bool y
select [31mCONFIG_STACKTRACE[0m
config [31mCONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE[0m
def_bool y
depends on [31mCONFIG_ARC_MMU_V4[0m
menu "ARC Architecture Configuration"
menu "ARC Platform/SoC/Board"
source "arch/arc/plat-tb10x/Kconfig"
source "arch/arc/plat-axs10x/Kconfig"
#New platform adds here
source "arch/arc/plat-eznps/Kconfig"
source "arch/arc/plat-hsdk/Kconfig"
endmenu
choice
prompt "ARC Instruction Set"
default [31mCONFIG_ISA_ARCV2[0m
config [31mCONFIG_ISA_ARCOMPACT[0m
bool "ARCompact ISA"
select [31mCONFIG_CPU_NO_EFFICIENT_FFS[0m
help
The original [31mCONFIG_ARC[0m [31mCONFIG_ISA[0m of ARC600/700 cores
config [31mCONFIG_ISA_ARCV2[0m
bool "ARC ISA v2"
select [31mCONFIG_ARC_TIMERS_64BIT[0m
help
[31mCONFIG_ISA[0m for the Next Generation [31mCONFIG_ARC[0m-HS cores
endchoice
menu "ARC CPU Configuration"
choice
prompt "ARC Core"
default [31mCONFIG_ARC_CPU_770[0m if [31mCONFIG_ISA_ARCOMPACT[0m
default [31mCONFIG_ARC_CPU_HS[0m if [31mCONFIG_ISA_ARCV2[0m
if [31mCONFIG_ISA_ARCOMPACT[0m
config [31mCONFIG_ARC_CPU_750D[0m
bool "ARC750D"
select [31mCONFIG_ARC_CANT_LLSC[0m
help
Support for ARC750 core
config [31mCONFIG_ARC_CPU_770[0m
bool "ARC770"
select [31mCONFIG_ARC_HAS_SWAPE[0m
help
Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
This core has a bunch of cool new features:
-[31mCONFIG_MMU[0m-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
Shared Address Spaces (for sharing TLB entries in [31mCONFIG_MMU[0m)
-Caches: New Prog Model, Region Flush
-Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
endif #[31mCONFIG_ISA_ARCOMPACT[0m
config [31mCONFIG_ARC_CPU_HS[0m
bool "ARC-HS"
depends on [31mCONFIG_ISA_ARCV2[0m
help
Support for [31mCONFIG_ARC[0m HS38x Cores based on ARCv2 [31mCONFIG_ISA[0m
The notable features are:
- [31mCONFIG_SMP[0m configurations of upto 4 core with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
endchoice
config [31mCONFIG_CPU_BIG_ENDIAN[0m
bool "Enable Big Endian Mode"
help
Build kernel for Big Endian Mode of [31mCONFIG_ARC[0m CPU
config [31mCONFIG_SMP[0m
bool "Symmetric Multi-Processing"
select [31mCONFIG_ARC_MCIP[0m if [31mCONFIG_ISA_ARCV2[0m
help
This enables support for systems with more than one CPU.
if [31mCONFIG_SMP[0m
config [31mCONFIG_NR_CPUS[0m
int "Maximum number of CPUs (2-4096)"
range 2 4096
default "4"
config [31mCONFIG_ARC_SMP_HALT_ON_RESET[0m
bool "Enable Halt-on-reset boot mode"
help
In [31mCONFIG_SMP[0m configuration cores can be configured as Halt-on-reset
or they could all start at same time. For Halt-on-reset, non
masters are parked until Master kicks them so they can start of
at designated entry point. For other case, all jump to common
entry point and spin wait for Master's signal.
endif #[31mCONFIG_SMP[0m
config [31mCONFIG_ARC_MCIP[0m
bool "ARConnect Multicore IP (MCIP) Support "
depends on [31mCONFIG_ISA_ARCV2[0m
default y if [31mCONFIG_SMP[0m
help
This IP block enables [31mCONFIG_SMP[0m in [31mCONFIG_ARC[0m-HS38 cores.
It provides for cross-core interrupts, multi-core debug
hardware semaphores, shared memory,....
menuconfig [31mCONFIG_ARC_CACHE[0m
bool "Enable Cache Support"
default y
if [31mCONFIG_ARC_CACHE[0m
config [31mCONFIG_ARC_CACHE_LINE_SHIFT[0m
int "Cache Line Length (as power of 2)"
range 5 7
default "6"
help
Starting with ARC700 4.9, Cache line length is configurable,
This option specifies "N", with Line-len = 2 power N
So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
Linux only supports same line lengths for I and [31mCONFIG_D[0m caches.
config [31mCONFIG_ARC_HAS_ICACHE[0m
bool "Use Instruction Cache"
default y
config [31mCONFIG_ARC_HAS_DCACHE[0m
bool "Use Data Cache"
default y
config [31mCONFIG_ARC_CACHE_PAGES[0m
bool "Per Page Cache Control"
default y
depends on [31mCONFIG_ARC_HAS_ICACHE[0m || [31mCONFIG_ARC_HAS_DCACHE[0m
help
This can be used to over-ride the global I/[31mCONFIG_D[0m Cache Enable on a
per-page basis (but only for pages accessed via [31mCONFIG_MMU[0m such as
Kernel Virtual address or User Virtual Address)
TLB entries have a per-page Cache Enable Bit.
Note that Global I/[31mCONFIG_D[0m ENABLE + Per Page DISABLE works but corollary
Global DISABLE + Per Page ENABLE won't work
config [31mCONFIG_ARC_CACHE_VIPT_ALIASING[0m
bool "Support VIPT Aliasing D$"
depends on [31mCONFIG_ARC_HAS_DCACHE[0m && [31mCONFIG_ISA_ARCOMPACT[0m
endif #[31mCONFIG_ARC_CACHE[0m
config [31mCONFIG_ARC_HAS_ICCM[0m
bool "Use ICCM"
help
Single Cycle RAMS to store Fast Path Code
config [31mCONFIG_ARC_ICCM_SZ[0m
int "ICCM Size in KB"
default "64"
depends on [31mCONFIG_ARC_HAS_ICCM[0m
config [31mCONFIG_ARC_HAS_DCCM[0m
bool "Use DCCM"
help
Single Cycle RAMS to store Fast Path Data
config [31mCONFIG_ARC_DCCM_SZ[0m
int "DCCM Size in KB"
default "64"
depends on [31mCONFIG_ARC_HAS_DCCM[0m
config [31mCONFIG_ARC_DCCM_BASE[0m
hex "DCCM map address"
default "0xA0000000"
depends on [31mCONFIG_ARC_HAS_DCCM[0m
choice
prompt "MMU Version"
default [31mCONFIG_ARC_MMU_V3[0m if [31mCONFIG_ARC_CPU_770[0m
default [31mCONFIG_ARC_MMU_V2[0m if [31mCONFIG_ARC_CPU_750D[0m
default [31mCONFIG_ARC_MMU_V4[0m if [31mCONFIG_ARC_CPU_HS[0m
if [31mCONFIG_ISA_ARCOMPACT[0m
config [31mCONFIG_ARC_MMU_V1[0m
bool "MMU v1"
help
Orig ARC700 [31mCONFIG_MMU[0m
config [31mCONFIG_ARC_MMU_V2[0m
bool "MMU v2"
help
Fixed the deficiency of v1 - possible thrashing in memcpy scenario
when 2 [31mCONFIG_D[0m-TLB and 1 I-TLB entries index into same 2way set.
config [31mCONFIG_ARC_MMU_V3[0m
bool "MMU v3"
depends on [31mCONFIG_ARC_CPU_770[0m
help
Introduced with ARC700 4.10: New Features
Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
Shared Address Spaces (SASID)
endif
config [31mCONFIG_ARC_MMU_V4[0m
bool "MMU v4"
depends on [31mCONFIG_ISA_ARCV2[0m
endchoice
choice
prompt "MMU Page Size"
default [31mCONFIG_ARC_PAGE_SIZE_8K[0m
config [31mCONFIG_ARC_PAGE_SIZE_8K[0m
bool "8KB"
help
Choose between 8k vs 16k
config [31mCONFIG_ARC_PAGE_SIZE_16K[0m
bool "16KB"
depends on [31mCONFIG_ARC_MMU_V3[0m || [31mCONFIG_ARC_MMU_V4[0m
config [31mCONFIG_ARC_PAGE_SIZE_4K[0m
bool "4KB"
depends on [31mCONFIG_ARC_MMU_V3[0m || [31mCONFIG_ARC_MMU_V4[0m
endchoice
choice
prompt "MMU Super Page Size"
depends on [31mCONFIG_ISA_ARCV2[0m && [31mCONFIG_TRANSPARENT_HUGEPAGE[0m
default [31mCONFIG_ARC_HUGEPAGE_2M[0m
config [31mCONFIG_ARC_HUGEPAGE_2M[0m
bool "2MB"
config [31mCONFIG_ARC_HUGEPAGE_16M[0m
bool "16MB"
endchoice
config [31mCONFIG_NODES_SHIFT[0m
int "Maximum NUMA Nodes (as a power of 2)"
default "0" if ![31mCONFIG_DISCONTIGMEM[0m
default "1" if [31mCONFIG_DISCONTIGMEM[0m
depends on [31mCONFIG_NEED_MULTIPLE_NODES[0m
---help---
Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
zones.
if [31mCONFIG_ISA_ARCOMPACT[0m
config [31mCONFIG_ARC_COMPACT_IRQ_LEVELS[0m
bool "Setup Timer IRQ as high Priority"
# if [31mCONFIG_SMP[0m, LV2 enabled ONLY if [31mCONFIG_ARC[0m implementation has LV2 re-entrancy
depends on ![31mCONFIG_SMP[0m
config [31mCONFIG_ARC_FPU_SAVE_RESTORE[0m
bool "Enable FPU state persistence across context switch"
help
Double Precision Floating Point unit had dedicated regs which
need to be saved/restored across context-switch.
Note that [31mCONFIG_ARC[0m [31mCONFIG_FPU[0m is overly simplistic, unlike say x86, which has
hardware pieces to allow software to conditionally save/restore,
based on actual usage of [31mCONFIG_FPU[0m by a task. Thus our implemn does
this for all tasks in system.
endif #[31mCONFIG_ISA_ARCOMPACT[0m
config [31mCONFIG_ARC_CANT_LLSC[0m
def_bool n
config [31mCONFIG_ARC_HAS_LLSC[0m
bool "Insn: LLOCK/SCOND (efficient atomic ops)"
default y
depends on ![31mCONFIG_ARC_CANT_LLSC[0m
config [31mCONFIG_ARC_HAS_SWAPE[0m
bool "Insn: SWAPE (endian-swap)"
default y
if [31mCONFIG_ISA_ARCV2[0m
config [31mCONFIG_ARC_USE_UNALIGNED_MEM_ACCESS[0m
bool "Enable unaligned access in HW"
default y
select [31mCONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS[0m
help
The [31mCONFIG_ARC[0m HS architecture supports unaligned memory access
which is disabled by default. Enable unaligned access in
hardware and use software to use it
config [31mCONFIG_ARC_HAS_LL64[0m
bool "Insn: 64bit LDD/STD"
help
Enable gcc to generate 64-bit load/store instructions
[31mCONFIG_ISA[0m mandates even/odd registers to allow encoding of two
dest operands with 2 possible source operands.
default y
config [31mCONFIG_ARC_HAS_DIV_REM[0m
bool "Insn: div, divu, rem, remu"
default y
config [31mCONFIG_ARC_HAS_ACCL_REGS[0m
bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
default y
help
Depending on the configuration, CPU can contain accumulator reg-pair
(also referred to as r58:r59). These can also be used by gcc as GPR so
kernel needs to save/restore per process
config [31mCONFIG_ARC_IRQ_NO_AUTOSAVE[0m
bool "Disable hardware autosave regfile on interrupts"
default n
help
On HS cores, taken interrupt auto saves the regfile on stack.
This is programmable and can be optionally disabled in which case
software INTERRUPT_PROLOGUE/EPILGUE do the needed work
endif # [31mCONFIG_ISA_ARCV2[0m
endmenu # "ARC CPU Configuration"
config [31mCONFIG_LINUX_LINK_BASE[0m
hex "Kernel link address"
default "0x80000000"
help
ARC700 divides the 32 bit phy address space into two equal halves
-Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by [31mCONFIG_MMU[0m
-Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
Typically Linux kernel is linked at the start of untransalted addr,
hence the default value of 0x8zs.
However some customers have peripherals mapped at this addr, so
Linux needs to be scooted a bit.
If you don't know what the above means, leave this setting alone.
This needs to match memory start address specified in Device Tree
config [31mCONFIG_LINUX_RAM_BASE[0m
hex "RAM base address"
default [31mCONFIG_LINUX_LINK_BASE[0m
help
By default Linux is linked at base of RAM. However in some special
cases (such as HSDK), Linux can't be linked at start of [31mCONFIG_DDR[0m, hence
this option.
config [31mCONFIG_HIGHMEM[0m
bool "High Memory Support"
select [31mCONFIG_ARCH_DISCONTIGMEM_ENABLE[0m
help
With [31mCONFIG_ARC[0m 2G:2G address split, only upper 2G is directly addressable by
kernel. Enable this to potentially allow access to rest of 2G and PAE
in future
config [31mCONFIG_ARC_HAS_PAE40[0m
bool "Support for the 40-bit Physical Address Extension"
depends on [31mCONFIG_ISA_ARCV2[0m
select [31mCONFIG_HIGHMEM[0m
select [31mCONFIG_PHYS_ADDR_T_64BIT[0m
help
Enable access to physical memory beyond 4G, only supported on
[31mCONFIG_ARC[0m cores with 40 bit Physical Addressing support
config [31mCONFIG_ARC_KVADDR_SIZE[0m
int "Kernel Virtual Address Space size (MB)"
range 0 512
default "256"
help
The kernel address space is carved out of 256MB of translated address
space for catering to vmalloc, modules, pkmap, fixmap. This however may
not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
this to be stretched to 512 MB (by extending into the reserved
kernel-user gutter)
config [31mCONFIG_ARC_CURR_IN_REG[0m
bool "Dedicate Register r25 for current_task pointer"
default y
help
This reserved Register R25 to point to Current Task in
kernel mode. This saves memory access for each such access
config [31mCONFIG_ARC_EMUL_UNALIGNED[0m
bool "Emulate unaligned memory access (userspace only)"
select [31mCONFIG_SYSCTL_ARCH_UNALIGN_NO_WARN[0m
select [31mCONFIG_SYSCTL_ARCH_UNALIGN_ALLOW[0m
depends on [31mCONFIG_ISA_ARCOMPACT[0m
help
This enables misaligned 16 & 32 bit memory access from user space.
Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
potential bugs in code
config [31mCONFIG_HZ[0m
int "Timer Frequency"
default 100
config [31mCONFIG_ARC_METAWARE_HLINK[0m
bool "Support for Metaware debugger assisted Host access"
help
This options allows a Linux userland apps to directly access
host file system (open/creat/read/write etc) with help from
Metaware Debugger. This can come in handy for Linux-host communication
when there is no real usable peripheral such as EMAC.
menuconfig [31mCONFIG_ARC_DBG[0m
bool "ARC debugging"
default y
if [31mCONFIG_ARC_DBG[0m
config [31mCONFIG_ARC_DW2_UNWIND[0m
bool "Enable DWARF specific kernel stack unwind"
default y
select [31mCONFIG_KALLSYMS[0m
help
Compiles the kernel with DWARF unwind information and can be used
to get stack backtraces.
If you say Y here the resulting kernel image will be slightly larger
but not slower, and it will give very useful debugging information.
If you don't debug the kernel, you can say N, but we may not be able
to solve problems without frame unwind information
config [31mCONFIG_ARC_DBG_TLB_PARANOIA[0m
bool "Paranoia Checks in Low Level TLB Handlers"
endif
config [31mCONFIG_ARC_BUILTIN_DTB_NAME[0m
string "Built in DTB"
help
Set the name of the DTB to embed in the vmlinux binary
Leaving it blank selects the minimal "skeleton" dtb
endmenu # "ARC Architecture Configuration"
config [31mCONFIG_FORCE_MAX_ZONEORDER[0m
int "Maximum zone order"
default "12" if [31mCONFIG_ARC_HUGEPAGE_16M[0m
default "11"
source "kernel/power/Kconfig"