# SPDX-License-Identifier: GPL-2.0 # # Makefile for the fpga framework and fpga manager drivers. # # Core FPGA Manager Framework obj-$([31mCONFIG_FPGA[0m) += fpga-mgr.o # FPGA Manager Drivers obj-$([31mCONFIG_FPGA_MGR_ALTERA_CVP[0m) += altera-cvp.o obj-$([31mCONFIG_FPGA_MGR_ALTERA_PS_SPI[0m) += altera-ps-spi.o obj-$([31mCONFIG_FPGA_MGR_ICE40_SPI[0m) += ice40-spi.o obj-$([31mCONFIG_FPGA_MGR_MACHXO2_SPI[0m) += machxo2-spi.o obj-$([31mCONFIG_FPGA_MGR_SOCFPGA[0m) += socfpga.o obj-$([31mCONFIG_FPGA_MGR_SOCFPGA_A10[0m) += socfpga-a10.o obj-$([31mCONFIG_FPGA_MGR_STRATIX10_SOC[0m) += stratix10-soc.o obj-$([31mCONFIG_FPGA_MGR_TS73XX[0m) += ts73xx-fpga.o obj-$([31mCONFIG_FPGA_MGR_XILINX_SPI[0m) += xilinx-spi.o obj-$([31mCONFIG_FPGA_MGR_ZYNQ_FPGA[0m) += zynq-fpga.o obj-$([31mCONFIG_FPGA_MGR_ZYNQMP_FPGA[0m) += zynqmp-fpga.o obj-$([31mCONFIG_ALTERA_PR_IP_CORE[0m) += altera-pr-ip-core.o obj-$([31mCONFIG_ALTERA_PR_IP_CORE_PLAT[0m) += altera-pr-ip-core-plat.o # FPGA Bridge Drivers obj-$([31mCONFIG_FPGA_BRIDGE[0m) += fpga-bridge.o obj-$([31mCONFIG_SOCFPGA_FPGA_BRIDGE[0m) += altera-hps2fpga.o altera-fpga2sdram.o obj-$([31mCONFIG_ALTERA_FREEZE_BRIDGE[0m) += altera-freeze-bridge.o obj-$([31mCONFIG_XILINX_PR_DECOUPLER[0m) += xilinx-pr-decoupler.o # High Level Interfaces obj-$([31mCONFIG_FPGA_REGION[0m) += fpga-region.o obj-$([31mCONFIG_OF_FPGA_REGION[0m) += of-fpga-region.o # FPGA Device Feature List Support obj-$([31mCONFIG_FPGA_DFL[0m) += dfl.o obj-$([31mCONFIG_FPGA_DFL_FME[0m) += dfl-fme.o obj-$([31mCONFIG_FPGA_DFL_FME_MGR[0m) += dfl-fme-mgr.o obj-$([31mCONFIG_FPGA_DFL_FME_BRIDGE[0m) += dfl-fme-br.o obj-$([31mCONFIG_FPGA_DFL_FME_REGION[0m) += dfl-fme-region.o obj-$([31mCONFIG_FPGA_DFL_AFU[0m) += dfl-afu.o dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o dfl-afu-objs += dfl-afu-error.o # Drivers for FPGAs which implement DFL obj-$([31mCONFIG_FPGA_DFL_PCI[0m) += dfl-pci.o |