[
    {
        "EventCode": "0x11",
        "EventName": "CPU_CYCLES",
        "BriefDescription": "The number of core clock cycles."
    },
    {
        "PublicDescription": "Bus access. This event counts for every beat of data transferred over the data channels between the core and the SCU. If both read and write data beats are transferred on a given cycle, this event is counted twice on that cycle. This event counts the sum of BUS_ACCESS_RD and BUS_ACCESS_WR.",
        "EventCode": "0x19",
        "EventName": "BUS_ACCESS",
        "BriefDescription": "Bus access."
    },
    {
        "EventCode": "0x1D",
        "EventName": "BUS_CYCLES",
        "BriefDescription": "Bus cycles. This event duplicates CPU_CYCLES."
    },
    {
        "ArchStdEvent":  "BUS_ACCESS_RD"
    },
    {
        "ArchStdEvent":  "BUS_ACCESS_WR"
    }
]