Training courses

Kernel and Embedded Linux

Bootlin training courses

Embedded Linux, kernel,
Yocto Project, Buildroot, real-time,
graphics, boot time, debugging...

Bootlin logo

Elixir Cross Referencer

Open Menu /tools/perf/pmu-events/arch/x86/sandybridge/other.json 
 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
[
    {
        "EventCode": "0x17",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Valid instructions written to IQ per cycle.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x4E",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "HW_PRE_REQ.DL1_MISS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5C",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "CPL_CYCLES.RING0",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5C",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EdgeDetect": "1",
        "EventName": "CPL_CYCLES.RING0_TRANS",
        "SampleAfterValue": "100007",
        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5C",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "CPL_CYCLES.RING123",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x63",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    }
]