[ { "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x04", "EventName": "LLC_MISSES.MEM_READ", "PerPkg": "1", "ScaleUnit": "64Bytes", "UMask": "0x0f", "Unit": "iMC" }, { "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x04", "EventName": "LLC_MISSES.MEM_WRITE", "PerPkg": "1", "ScaleUnit": "64Bytes", "UMask": "0x30", "Unit": "iMC" }, { "BriefDescription": "Memory controller clock ticks", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Pre-charge for reads", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.RD", "PerPkg": "1", "UMask": "0x04", "Unit": "iMC" }, { "BriefDescription": "Pre-charge for writes", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.WR", "PerPkg": "1", "UMask": "0x08", "Unit": "iMC" }, { "BriefDescription": "Precharge due to read on page miss, write on page miss or PGT", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.ALL", "PerPkg": "1", "UMask": "0x1c", "Unit": "iMC" }, { "BriefDescription": "DRAM Precharge commands. : Precharge due to page table", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.PGT", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel.", "UMask": "0x10", "Unit": "iMC" } ] |