# SPDX-License-Identifier: GPL-2.0
config [31mCONFIG_XTENSA[0m
def_bool y
select [31mCONFIG_ARCH_32BIT_OFF_T[0m
select [31mCONFIG_ARCH_HAS_BINFMT_FLAT[0m if ![31mCONFIG_MMU[0m
select [31mCONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU[0m
select [31mCONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE[0m
select [31mCONFIG_ARCH_USE_QUEUED_RWLOCKS[0m
select [31mCONFIG_ARCH_USE_QUEUED_SPINLOCKS[0m
select [31mCONFIG_ARCH_WANT_FRAME_POINTERS[0m
select [31mCONFIG_ARCH_WANT_IPC_PARSE_VERSION[0m
select [31mCONFIG_BUILDTIME_EXTABLE_SORT[0m
select [31mCONFIG_CLONE_BACKWARDS[0m
select [31mCONFIG_COMMON_CLK[0m
select [31mCONFIG_DMA_REMAP[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_GENERIC_ATOMIC64[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_GENERIC_IRQ_SHOW[0m
select [31mCONFIG_GENERIC_PCI_IOMAP[0m
select [31mCONFIG_GENERIC_SCHED_CLOCK[0m
select [31mCONFIG_GENERIC_STRNCPY_FROM_USER[0m if [31mCONFIG_KASAN[0m
select [31mCONFIG_HAVE_ARCH_JUMP_LABEL[0m
select [31mCONFIG_HAVE_ARCH_KASAN[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_HAVE_ARCH_TRACEHOOK[0m
select [31mCONFIG_HAVE_DEBUG_KMEMLEAK[0m
select [31mCONFIG_HAVE_DMA_CONTIGUOUS[0m
select [31mCONFIG_HAVE_EXIT_THREAD[0m
select [31mCONFIG_HAVE_FUNCTION_TRACER[0m
select [31mCONFIG_HAVE_FUTEX_CMPXCHG[0m if ![31mCONFIG_MMU[0m
select [31mCONFIG_HAVE_HW_BREAKPOINT[0m if [31mCONFIG_PERF_EVENTS[0m
select [31mCONFIG_HAVE_IRQ_TIME_ACCOUNTING[0m
select [31mCONFIG_HAVE_OPROFILE[0m
select [31mCONFIG_HAVE_PCI[0m
select [31mCONFIG_HAVE_PERF_EVENTS[0m
select [31mCONFIG_HAVE_STACKPROTECTOR[0m
select [31mCONFIG_HAVE_SYSCALL_TRACEPOINTS[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_MODULES_USE_ELF_RELA[0m
select [31mCONFIG_PERF_USE_VMALLOC[0m
select [31mCONFIG_VIRT_TO_BUS[0m
help
Xtensa processors are 32-bit RISC machines designed by Tensilica
primarily for embedded systems. These processors are both
configurable and extensible. The Linux port to the Xtensa
architecture supports all processor configurations and extensions,
with reasonable minimum requirements. The Xtensa Linux project has
a home page at <http://www.linux-xtensa.org/>.
config [31mCONFIG_GENERIC_HWEIGHT[0m
def_bool y
config [31mCONFIG_ARCH_HAS_ILOG2_U32[0m
def_bool n
config [31mCONFIG_ARCH_HAS_ILOG2_U64[0m
def_bool n
config [31mCONFIG_NO_IOPORT_MAP[0m
def_bool n
config [31mCONFIG_HZ[0m
int
default 100
config [31mCONFIG_LOCKDEP_SUPPORT[0m
def_bool y
config [31mCONFIG_STACKTRACE_SUPPORT[0m
def_bool y
config [31mCONFIG_TRACE_IRQFLAGS_SUPPORT[0m
def_bool y
config [31mCONFIG_MMU[0m
def_bool n
config [31mCONFIG_HAVE_XTENSA_GPIO32[0m
def_bool n
config [31mCONFIG_KASAN_SHADOW_OFFSET[0m
hex
default 0x6e400000
menu "Processor type and features"
choice
prompt "Xtensa Processor Configuration"
default [31mCONFIG_XTENSA_VARIANT_FSF[0m
config [31mCONFIG_XTENSA_VARIANT_FSF[0m
bool "fsf - default (not generic) configuration"
select [31mCONFIG_MMU[0m
config [31mCONFIG_XTENSA_VARIANT_DC232B[0m
bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
select [31mCONFIG_MMU[0m
select [31mCONFIG_HAVE_XTENSA_GPIO32[0m
help
This variant refers to Tensilica's Diamond 232L Standard core Rev.[31mCONFIG_B[0m (LE).
config [31mCONFIG_XTENSA_VARIANT_DC233C[0m
bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
select [31mCONFIG_MMU[0m
select [31mCONFIG_HAVE_XTENSA_GPIO32[0m
help
This variant refers to Tensilica's Diamond 233L Standard core Rev.[31mCONFIG_C[0m (LE).
config [31mCONFIG_XTENSA_VARIANT_CUSTOM[0m
bool "Custom Xtensa processor configuration"
select [31mCONFIG_HAVE_XTENSA_GPIO32[0m
help
Select this variant to use a custom Xtensa processor configuration.
You will be prompted for a processor variant CORENAME.
endchoice
config [31mCONFIG_XTENSA_VARIANT_CUSTOM_NAME[0m
string "Xtensa Processor Custom Core Variant Name"
depends on [31mCONFIG_XTENSA_VARIANT_CUSTOM[0m
help
Provide the name of a custom Xtensa processor variant.
This CORENAME selects arch/xtensa/variant/CORENAME.
Dont forget you have to select [31mCONFIG_MMU[0m if you have one.
config [31mCONFIG_XTENSA_VARIANT_NAME[0m
string
default "dc232b" if [31mCONFIG_XTENSA_VARIANT_DC232B[0m
default "dc233c" if [31mCONFIG_XTENSA_VARIANT_DC233C[0m
default "fsf" if [31mCONFIG_XTENSA_VARIANT_FSF[0m
default [31mCONFIG_XTENSA_VARIANT_CUSTOM_NAME[0m if [31mCONFIG_XTENSA_VARIANT_CUSTOM[0m
config [31mCONFIG_XTENSA_VARIANT_MMU[0m
bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
depends on [31mCONFIG_XTENSA_VARIANT_CUSTOM[0m
default y
select [31mCONFIG_MMU[0m
help
Build a Conventional Kernel with full [31mCONFIG_MMU[0m support,
ie: it supports a TLB with auto-loading, page protection.
config [31mCONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS[0m
bool "Core variant has Performance Monitor Module"
depends on [31mCONFIG_XTENSA_VARIANT_CUSTOM[0m
default n
help
Enable if core variant has Performance Monitor Module with
External Registers Interface.
If unsure, say N.
config [31mCONFIG_XTENSA_FAKE_NMI[0m
bool "Treat PMM IRQ as NMI"
depends on [31mCONFIG_XTENSA_VARIANT_HAVE_PERF_EVENTS[0m
default n
help
If PMM IRQ is the only IRQ at EXCM level it is safe to
treat it as NMI, which improves accuracy of profiling.
If there are other interrupts at or above PMM IRQ priority level
but not above the EXCM level, PMM IRQ still may be treated as NMI,
but only if these IRQs are not used. There will be a build warning
saying that this is not safe, and a bugcheck if one of these IRQs
actually fire.
If unsure, say N.
config [31mCONFIG_XTENSA_UNALIGNED_USER[0m
bool "Unaligned memory access in user space"
help
The Xtensa architecture currently does not handle unaligned
memory accesses in hardware but through an exception handler.
Per default, unaligned memory accesses are disabled in user space.
Say Y here to enable unaligned memory access in user space.
config [31mCONFIG_HAVE_SMP[0m
bool "System Supports SMP (MX)"
depends on [31mCONFIG_XTENSA_VARIANT_CUSTOM[0m
select [31mCONFIG_XTENSA_MX[0m
help
This option is use to indicate that the system-on-a-chip (SOC)
supports Multiprocessing. Multiprocessor support implemented above
the CPU core definition and currently needs to be selected manually.
Multiprocessor support in implemented with external cache and
interrupt controllers.
The MX interrupt distributer adds Interprocessor Interrupts
and causes the IRQ numbers to be increased by 4 for devices
like the open cores ethernet driver and the serial interface.
You still have to select "Enable SMP" to enable [31mCONFIG_SMP[0m on this SOC.
config [31mCONFIG_SMP[0m
bool "Enable Symmetric multi-processing support"
depends on [31mCONFIG_HAVE_SMP[0m
select [31mCONFIG_GENERIC_SMP_IDLE_THREAD[0m
help
Enabled [31mCONFIG_SMP[0m Software; allows more than one CPU/[31mCONFIG_CORE[0m
to be activated during startup.
config [31mCONFIG_NR_CPUS[0m
depends on [31mCONFIG_SMP[0m
int "Maximum number of CPUs (2-32)"
range 2 32
default "4"
config [31mCONFIG_HOTPLUG_CPU[0m
bool "Enable CPU hotplug support"
depends on [31mCONFIG_SMP[0m
help
Say Y here to allow turning CPUs off and on. CPUs can be
controlled through /sys/devices/system/cpu.
Say N if you want to disable CPU hotplug.
config [31mCONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX[0m
bool "Initialize Xtensa MMU inside the Linux kernel code"
depends on ![31mCONFIG_XTENSA_VARIANT_FSF[0m && ![31mCONFIG_XTENSA_VARIANT_DC232B[0m
default y if [31mCONFIG_XTENSA_VARIANT_DC233C[0m || [31mCONFIG_XTENSA_VARIANT_CUSTOM[0m
help
Earlier version initialized the [31mCONFIG_MMU[0m in the exception vector
before jumping to _startup in head.S and had an advantage that
it was possible to place a software breakpoint at 'reset' and
then enter your normal kernel breakpoints once the [31mCONFIG_MMU[0m was mapped
to the kernel mappings (0XC0000000).
This unfortunately won't work for U-Boot and likely also wont
work for using [31mCONFIG_KEXEC[0m to have a hot kernel ready for doing a
KDUMP.
So now the [31mCONFIG_MMU[0m is initialized in head.S but it's necessary to
use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup.
xt-gdb can't place a Software Breakpoint in the 0XD region prior
to mapping the [31mCONFIG_MMU[0m and after mapping even if the area of low memory
was mapped gdb wouldn't remove the breakpoint on hitting it as the
PC wouldn't match. Since Hardware Breakpoints are recommended for
Linux configurations it seems reasonable to just assume they exist
and leave this older mechanism for unfortunate souls that choose
not to follow Tensilica's recommendation.
Selecting this will cause U-Boot to set the KERNEL Load and Entry
address at 0x00003000 instead of the mapped std of 0xD0003000.
If in doubt, say Y.
config [31mCONFIG_MEMMAP_CACHEATTR[0m
hex "Cache attributes for the memory address space"
depends on ![31mCONFIG_MMU[0m
default 0x22222222
help
These cache attributes are set up for noMMU systems. Each hex digit
specifies cache attributes for the corresponding 512MB memory
region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
Cache attribute values are specific for the [31mCONFIG_MMU[0m type.
For region protection MMUs:
1: WT cached,
2: cache bypass,
4: WB cached,
f: illegal.
For ful [31mCONFIG_MMU[0m:
bit 0: executable,
bit 1: writable,
bits 2..3:
0: cache bypass,
1: WB cache,
2: WT cache,
3: special (c and e are illegal, f is reserved).
For [31mCONFIG_MPU[0m:
0: illegal,
1: WB cache,
2: WB, no-write-allocate cache,
3: WT cache,
4: cache bypass.
config [31mCONFIG_KSEG_PADDR[0m
hex "Physical address of the KSEG mapping"
depends on [31mCONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX[0m && [31mCONFIG_MMU[0m
default 0x00000000
help
This is the physical address where KSEG is mapped. Please refer to
the chosen KSEG layout help for the required address alignment.
Unpacked kernel image (including vectors) must be located completely
within KSEG.
Physical memory below this address is not available to linux.
If unsure, leave the default value here.
config [31mCONFIG_KERNEL_LOAD_ADDRESS[0m
hex "Kernel load address"
default 0x60003000 if ![31mCONFIG_MMU[0m
default 0x00003000 if [31mCONFIG_MMU[0m && [31mCONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX[0m
default 0xd0003000 if [31mCONFIG_MMU[0m && ![31mCONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX[0m
help
This is the address where the kernel is loaded.
It is virtual address for MMUv2 configurations and physical address
for all other configurations.
If unsure, leave the default value here.
config [31mCONFIG_VECTORS_OFFSET[0m
hex "Kernel vectors offset"
default 0x00003000
help
This is the offset of the kernel image from the relocatable vectors
base.
If unsure, leave the default value here.
choice
prompt "KSEG layout"
depends on [31mCONFIG_MMU[0m
default [31mCONFIG_XTENSA_KSEG_MMU_V2[0m
config [31mCONFIG_XTENSA_KSEG_MMU_V2[0m
bool "MMUv2: 128MB cached + 128MB uncached"
help
MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
at [31mCONFIG_KSEG_PADDR[0m to 0xd0000000 with cache and to 0xd8000000
without cache.
[31mCONFIG_KSEG_PADDR[0m must be aligned to 128MB.
config [31mCONFIG_XTENSA_KSEG_256M[0m
bool "256MB cached + 256MB uncached"
depends on [31mCONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX[0m
help
TLB way 6 maps 256MB starting at [31mCONFIG_KSEG_PADDR[0m to 0xb0000000
with cache and to 0xc0000000 without cache.
[31mCONFIG_KSEG_PADDR[0m must be aligned to 256MB.
config [31mCONFIG_XTENSA_KSEG_512M[0m
bool "512MB cached + 512MB uncached"
depends on [31mCONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX[0m
help
TLB way 6 maps 512MB starting at [31mCONFIG_KSEG_PADDR[0m to 0xa0000000
with cache and to 0xc0000000 without cache.
[31mCONFIG_KSEG_PADDR[0m must be aligned to 256MB.
endchoice
config [31mCONFIG_HIGHMEM[0m
bool "High Memory Support"
depends on [31mCONFIG_MMU[0m
help
Linux can use the full amount of RAM in the system by
default. However, the default MMUv2 setup only maps the
lowermost 128 MB of memory linearly to the areas starting
at 0xd0000000 (cached) and 0xd8000000 (uncached).
When there are more than 128 MB memory in the system not
all of it can be "permanently mapped" by the kernel.
The physical memory that's not permanently mapped is called
"high memory".
If you are compiling a kernel which will never run on a
machine with more than 128 MB total physical RAM, answer
N here.
If unsure, say Y.
config [31mCONFIG_FAST_SYSCALL_XTENSA[0m
bool "Enable fast atomic syscalls"
default n
help
fast_syscall_xtensa is a syscall that can make atomic operations
on UP kernel when processor has no s32c1i support.
This syscall is deprecated. It may have issues when called with
invalid arguments. It is provided only for backwards compatibility.
Only enable it if your userspace software requires it.
If unsure, say N.
config [31mCONFIG_FAST_SYSCALL_SPILL_REGISTERS[0m
bool "Enable spill registers syscall"
default n
help
fast_syscall_spill_registers is a syscall that spills all active
register windows of a calling userspace task onto its stack.
This syscall is deprecated. It may have issues when called with
invalid arguments. It is provided only for backwards compatibility.
Only enable it if your userspace software requires it.
If unsure, say N.
config [31mCONFIG_USER_ABI_CALL0[0m
bool
choice
prompt "Userspace ABI"
default [31mCONFIG_USER_ABI_DEFAULT[0m
help
Select supported userspace ABI.
If unsure, choose the default ABI.
config [31mCONFIG_USER_ABI_DEFAULT[0m
bool "Default ABI only"
help
Assume default userspace ABI. For XEA2 cores it is windowed ABI.
call0 ABI binaries may be run on such kernel, but signal delivery
will not work correctly for them.
config [31mCONFIG_USER_ABI_CALL0_ONLY[0m
bool "Call0 ABI only"
select [31mCONFIG_USER_ABI_CALL0[0m
help
Select this option to support only call0 ABI in userspace.
Windowed ABI binaries will crash with a segfault caused by
an illegal instruction exception on the first 'entry' opcode.
Choose this option if you're planning to run only user code
built with call0 ABI.
config [31mCONFIG_USER_ABI_CALL0_PROBE[0m
bool "Support both windowed and call0 ABI by probing"
select [31mCONFIG_USER_ABI_CALL0[0m
help
Select this option to support both windowed and call0 userspace
ABIs. When enabled all processes are started with PS.WOE disabled
and a fast user exception handler for an illegal instruction is
used to turn on PS.WOE bit on the first 'entry' opcode executed by
the userspace.
This option should be enabled for the kernel that must support
both call0 and windowed ABIs in userspace at the same time.
Note that Xtensa [31mCONFIG_ISA[0m does not guarantee that entry opcode will
raise an illegal instruction exception on cores with XEA2 when
PS.WOE is disabled, check whether the target core supports it.
endchoice
endmenu
config [31mCONFIG_XTENSA_CALIBRATE_CCOUNT[0m
def_bool n
help
On some platforms (XT2000, for example), the CPU clock rate can
vary. The frequency can be determined, however, by measuring
against a well known, fixed frequency, such as an UART oscillator.
config [31mCONFIG_SERIAL_CONSOLE[0m
def_bool n
menu "Platform options"
choice
prompt "Xtensa System Type"
default [31mCONFIG_XTENSA_PLATFORM_ISS[0m
config [31mCONFIG_XTENSA_PLATFORM_ISS[0m
bool "ISS"
select [31mCONFIG_XTENSA_CALIBRATE_CCOUNT[0m
select [31mCONFIG_SERIAL_CONSOLE[0m
help
ISS is an acronym for Tensilica's Instruction Set Simulator.
config [31mCONFIG_XTENSA_PLATFORM_XT2000[0m
bool "XT2000"
select [31mCONFIG_HAVE_IDE[0m
help
XT2000 is the name of Tensilica's feature-rich emulation platform.
This hardware is capable of running a full Linux distribution.
config [31mCONFIG_XTENSA_PLATFORM_XTFPGA[0m
bool "XTFPGA"
select [31mCONFIG_ETHOC[0m if [31mCONFIG_ETHERNET[0m
select [31mCONFIG_PLATFORM_WANT_DEFAULT_MEM[0m if ![31mCONFIG_MMU[0m
select [31mCONFIG_SERIAL_CONSOLE[0m
select [31mCONFIG_XTENSA_CALIBRATE_CCOUNT[0m
help
XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
This hardware is capable of running a full Linux distribution.
endchoice
config [31mCONFIG_PLATFORM_NR_IRQS[0m
int
default 3 if [31mCONFIG_XTENSA_PLATFORM_XT2000[0m
default 0
config [31mCONFIG_XTENSA_CPU_CLOCK[0m
int "CPU clock rate [MHz]"
depends on ![31mCONFIG_XTENSA_CALIBRATE_CCOUNT[0m
default 16
config [31mCONFIG_GENERIC_CALIBRATE_DELAY[0m
bool "Auto calibration of the BogoMIPS value"
help
The BogoMIPS value can easily be derived from the CPU frequency.
config [31mCONFIG_CMDLINE_BOOL[0m
bool "Default bootloader kernel arguments"
config [31mCONFIG_CMDLINE[0m
string "Initial kernel command string"
depends on [31mCONFIG_CMDLINE_BOOL[0m
default "console=ttyS0,38400 root=/dev/ram"
help
On some architectures (EBSA110 and CATS), there is currently no way
for the boot loader to pass arguments to the kernel. For these
architectures, you should supply some command-line options at build
time by entering them here. As a minimum, you should specify the
memory size and the root device (e.g., mem=64M root=/dev/nfs).
config [31mCONFIG_USE_OF[0m
bool "Flattened Device Tree support"
select [31mCONFIG_OF[0m
select [31mCONFIG_OF_EARLY_FLATTREE[0m
help
Include support for flattened device tree machine descriptions.
config [31mCONFIG_BUILTIN_DTB_SOURCE[0m
string "DTB to build into the kernel image"
depends on [31mCONFIG_OF[0m
config [31mCONFIG_PARSE_BOOTPARAM[0m
bool "Parse bootparam block"
default y
help
Parse parameters passed to the kernel from the bootloader. It may
be disabled if the kernel is known to run without the bootloader.
If unsure, say Y.
config [31mCONFIG_BLK_DEV_SIMDISK[0m
tristate "Host file-based simulated block device support"
default n
depends on [31mCONFIG_XTENSA_PLATFORM_ISS[0m && [31mCONFIG_BLOCK[0m
help
Create block devices that map to files in the host file system.
Device binding to host file may be changed at runtime via proc
interface provided the device is not in use.
config [31mCONFIG_BLK_DEV_SIMDISK_COUNT[0m
int "Number of host file-based simulated block devices"
range 1 10
depends on [31mCONFIG_BLK_DEV_SIMDISK[0m
default 2
help
This is the default minimal number of created block devices.
Kernel/module parameter 'simdisk_count' may be used to change this
value at runtime. More file names (but no more than 10) may be
specified as parameters, simdisk_count grows accordingly.
config [31mCONFIG_SIMDISK0_FILENAME[0m
string "Host filename for the first simulated device"
depends on [31mCONFIG_BLK_DEV_SIMDISK[0m = y
default ""
help
Attach a first simdisk to a host file. Conventionally, this file
contains a root file system.
config [31mCONFIG_SIMDISK1_FILENAME[0m
string "Host filename for the second simulated device"
depends on [31mCONFIG_BLK_DEV_SIMDISK[0m = y && [31mCONFIG_BLK_DEV_SIMDISK_COUNT[0m != 1
default ""
help
Another simulated disk in a host file for a buildroot-independent
storage.
config [31mCONFIG_FORCE_MAX_ZONEORDER[0m
int "Maximum zone order"
default "11"
help
The kernel memory allocator divides physically contiguous memory
blocks into "zones", where each zone is a power of two number of
pages. This option selects the largest power of two that the kernel
keeps in the memory allocator. If you need to allocate very large
blocks of physically contiguous memory, then you may need to
increase this value.
This config option is actually maximum order plus one. For example,
a value of 11 means that the largest free memory block is 2^10 pages.
config [31mCONFIG_PLATFORM_WANT_DEFAULT_MEM[0m
def_bool n
config [31mCONFIG_DEFAULT_MEM_START[0m
hex
prompt "PAGE_OFFSET/PHYS_OFFSET" if ![31mCONFIG_MMU[0m && [31mCONFIG_PLATFORM_WANT_DEFAULT_MEM[0m
default 0x60000000 if [31mCONFIG_PLATFORM_WANT_DEFAULT_MEM[0m
default 0x00000000
help
This is the base address used for both [31mCONFIG_PAGE_OFFSET[0m and [31mCONFIG_PHYS_OFFSET[0m
in noMMU configurations.
If unsure, leave the default value here.
config [31mCONFIG_XTFPGA_LCD[0m
bool "Enable XTFPGA LCD driver"
depends on [31mCONFIG_XTENSA_PLATFORM_XTFPGA[0m
default n
help
There's a 2x16 LCD on most of XTFPGA boards, kernel may output
progress messages there during bootup/shutdown. It may be useful
during board bringup.
If unsure, say N.
config [31mCONFIG_XTFPGA_LCD_BASE_ADDR[0m
hex "XTFPGA LCD base address"
depends on [31mCONFIG_XTFPGA_LCD[0m
default "0x0d0c0000"
help
Base address of the LCD controller inside KIO region.
Different boards from XTFPGA family have LCD controller at different
addresses. Please consult prototyping user guide for your board for
the correct address. Wrong address here may lead to hardware lockup.
config [31mCONFIG_XTFPGA_LCD_8BIT_ACCESS[0m
bool "Use 8-bit access to XTFPGA LCD"
depends on [31mCONFIG_XTFPGA_LCD[0m
default n
help
LCD may be connected with 4- or 8-bit interface, 8-bit access may
only be used with 8-bit interface. Please consult prototyping user
guide for your board for the correct interface width.
endmenu
menu "Power management options"
source "kernel/power/Kconfig"
endmenu