Training courses

Kernel and Embedded Linux

Bootlin training courses

Embedded Linux, kernel,
Yocto Project, Buildroot, real-time,
graphics, boot time, debugging...

Bootlin logo

Elixir Cross Referencer

Open Menu /tools/perf/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json 
  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
[
    {
        "ArchStdEvent": "L1D_CACHE_RD",
    },
    {
        "ArchStdEvent": "L1D_CACHE_WR",
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_RD",
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_WR",
    },
    {
        "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
    },
    {
        "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
    },
    {
        "ArchStdEvent": "L1D_CACHE_INVAL",
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL_RD",
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL_WR",
    },
    {
        "ArchStdEvent": "L1D_TLB_RD",
    },
    {
        "ArchStdEvent": "L1D_TLB_WR",
    },
    {
        "ArchStdEvent": "L2D_CACHE_RD",
    },
    {
        "ArchStdEvent": "L2D_CACHE_WR",
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL_RD",
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL_WR",
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
    },
    {
        "ArchStdEvent": "L2D_CACHE_INVAL",
    },
    {
        "PublicDescription": "Level 1 instruction cache prefetch access count",
        "EventCode": "0x102e",
        "EventName": "L1I_CACHE_PRF",
        "BriefDescription": "L1I cache prefetch access count",
    },
    {
        "PublicDescription": "Level 1 instruction cache miss due to prefetch access count",
        "EventCode": "0x102f",
        "EventName": "L1I_CACHE_PRF_REFILL",
        "BriefDescription": "L1I cache miss due to prefetch access count",
    },
    {
        "PublicDescription": "Instruction queue is empty",
        "EventCode": "0x1043",
        "EventName": "IQ_IS_EMPTY",
        "BriefDescription": "Instruction queue is empty",
    },
    {
        "PublicDescription": "Instruction fetch stall cycles",
        "EventCode": "0x1044",
        "EventName": "IF_IS_STALL",
        "BriefDescription": "Instruction fetch stall cycles",
    },
    {
        "PublicDescription": "Instructions can receive, but not send",
        "EventCode": "0x2014",
        "EventName": "FETCH_BUBBLE",
        "BriefDescription": "Instructions can receive, but not send",
    },
    {
        "PublicDescription": "Prefetch request from LSU",
        "EventCode": "0x6013",
        "EventName": "PRF_REQ",
        "BriefDescription": "Prefetch request from LSU",
    },
    {
        "PublicDescription": "Hit on prefetched data",
        "EventCode": "0x6014",
        "EventName": "HIT_ON_PRF",
        "BriefDescription": "Hit on prefetched data",
    },
    {
        "PublicDescription": "Cycles of that the number of issuing micro operations are less than 4",
        "EventCode": "0x7001",
        "EventName": "EXE_STALL_CYCLE",
        "BriefDescription": "Cycles of that the number of issue ups are less than 4",
    },
    {
        "PublicDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
        "EventCode": "0x7004",
        "EventName": "MEM_STALL_ANYLOAD",
        "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved",
    },
    {
        "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
        "EventCode": "0x7006",
        "EventName": "MEM_STALL_L1MISS",
        "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill",
    },
    {
        "PublicDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
        "EventCode": "0x7007",
        "EventName": "MEM_STALL_L2MISS",
        "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache",
    },
]