Defined in 6 files as a macro:
- drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h, line 40 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h, line 51 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h, line 112 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h, line 238 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_offset.h, line 956 (as a macro)
- drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h, line 841 (as a macro)