STM32 Real Time Clock Required properties: - compatible: can be one of the following: - "st,stm32-rtc" for devices compatible with stm32(f4/f7). - "st,stm32h7-rtc" for devices compatible with stm32h7. - "st,stm32mp1-rtc" for devices compatible with stm32mp1. - reg: address range of rtc register set. - clocks: can use up to two clocks, depending on part used: - "rtc_ck": RTC clock source. - "pclk": RTC APB interface clock. It is not present on stm32(f4/f7). It is required on stm32(h7/mp1). - clock-names: must be "rtc_ck" and "pclk". It is required on stm32(h7/mp1). - interrupts: rtc alarm interrupt. On stm32mp1, a second interrupt is required for rtc alarm wakeup interrupt. - st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg used to access control register at offset, and change the dbp (Disable Backup Protection) bit represented by the mask, mandatory to disable/enable backup domain (RTC registers) write protection. It is required on stm32(f4/f7/h7). Optional properties (to override default rtc_ck parent clock on stm32(f4/f7/h7): - assigned-clocks: reference to the rtc_ck clock entry. - assigned-clock-parents: phandle of the new parent clock of rtc_ck. Example: rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; clocks = <&rcc 1 CLK_RTC>; assigned-clocks = <&rcc 1 CLK_RTC>; assigned-clock-parents = <&rcc 1 CLK_LSE>; interrupt-parent = <&exti>; interrupts = <17 1>; st,syscfg = <&pwrcfg 0x00 0x100>; }; rtc: rtc@58004000 { compatible = "st,stm32h7-rtc"; reg = <0x58004000 0x400>; clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; clock-names = "pclk", "rtc_ck"; assigned-clocks = <&rcc RTC_CK>; assigned-clock-parents = <&rcc LSE_CK>; interrupt-parent = <&exti>; interrupts = <17 1>; interrupt-names = "alarm"; st,syscfg = <&pwrcfg 0x00 0x100>; }; rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; clocks = <&rcc RTCAPB>, <&rcc RTC>; clock-names = "pclk", "rtc_ck"; interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_NONE>, <&exti 19 1>; }; |