# SPDX-License-Identifier: GPL-2.0 # # For a description of the syntax of this configuration file, # see Documentation/kbuild/kconfig-language.rst. # menuconfig [31mCONFIG_ARC_PLAT_EZNPS[0m bool "\"EZchip\" ARC dev platform" select [31mCONFIG_CPU_BIG_ENDIAN[0m select [31mCONFIG_CLKSRC_NPS[0m select [31mCONFIG_EZNPS_GIC[0m select [31mCONFIG_EZCHIP_NPS_MANAGEMENT_ENET[0m if [31mCONFIG_ETHERNET[0m help Support for EZchip development platforms, based on ARC700 cores. We handle few flavors: - Hardware Emulator AKA HE which is [31mCONFIG_FPGA[0m based chassis - Simulator based on MetaWare nSIM - NPS400 chip based on ASIC config [31mCONFIG_EZNPS_MTM_EXT[0m bool "ARC-EZchip MTM Extensions" select [31mCONFIG_CPUMASK_OFFSTACK[0m depends on [31mCONFIG_ARC_PLAT_EZNPS[0m && [31mCONFIG_SMP[0m default y help Here we add new hierarchy for CPUs topology. We got: Core Thread At the new thread level each CPU represent one HW thread. At highest hierarchy each core contain 16 threads, any of them seem like CPU from Linux point of view. All threads within same core share the execution unit of the core and HW scheduler round robin between them. config [31mCONFIG_EZNPS_MEM_ERROR_ALIGN[0m bool "ARC-EZchip Memory error as an exception" depends on [31mCONFIG_EZNPS_MTM_EXT[0m default n help On the real chip of the NPS, user memory errors are handled as a machine check exception, which is fatal, whereas on simulator platform for NPS, is handled as a Level 2 interrupt (just a stock ARC700) which is recoverable. This option makes simulator behave like hardware. config [31mCONFIG_EZNPS_SHARED_AUX_REGS[0m bool "ARC-EZchip Shared Auxiliary Registers Per Core" depends on [31mCONFIG_ARC_PLAT_EZNPS[0m default y help On the real chip of the NPS, auxiliary registers are shared between all the cpus of the core, whereas on simulator platform for NPS, each cpu has a different set of auxiliary registers. Configuration should be unset if auxiliary registers are not shared between the cpus of the core, so there will be a need to initialize them per cpu. |