# SPDX-License-Identifier: GPL-2.0-only
config CONFIG_ARM64
	def_bool y
	select CONFIG_ACPI_CCA_REQUIRED if CONFIG_ACPI
	select CONFIG_ACPI_GENERIC_GSI if CONFIG_ACPI
	select CONFIG_ACPI_GTDT if CONFIG_ACPI
	select CONFIG_ACPI_IORT if CONFIG_ACPI
	select CONFIG_ACPI_REDUCED_HARDWARE_ONLY if CONFIG_ACPI
	select CONFIG_ACPI_MCFG if (CONFIG_ACPI && CONFIG_PCI)
	select CONFIG_ACPI_SPCR_TABLE if CONFIG_ACPI
	select CONFIG_ACPI_PPTT if CONFIG_ACPI
	select CONFIG_ARCH_CLOCKSOURCE_DATA
	select CONFIG_ARCH_HAS_DEBUG_VIRTUAL
	select CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED
	select CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN
	select CONFIG_ARCH_HAS_DMA_PREP_COHERENT
	select CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE if CONFIG_ACPI
	select CONFIG_ARCH_HAS_FAST_MULTIPLIER
	select CONFIG_ARCH_HAS_FORTIFY_SOURCE
	select CONFIG_ARCH_HAS_GCOV_PROFILE_ALL
	select CONFIG_ARCH_HAS_GIGANTIC_PAGE
	select CONFIG_ARCH_HAS_KCOV
	select CONFIG_ARCH_HAS_KEEPINITRD
	select CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE
	select CONFIG_ARCH_HAS_PTE_DEVMAP
	select CONFIG_ARCH_HAS_PTE_SPECIAL
	select CONFIG_ARCH_HAS_SETUP_DMA_OPS
	select CONFIG_ARCH_HAS_SET_DIRECT_MAP
	select CONFIG_ARCH_HAS_SET_MEMORY
	select CONFIG_ARCH_HAS_STRICT_KERNEL_RWX
	select CONFIG_ARCH_HAS_STRICT_MODULE_RWX
	select CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE
	select CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU
	select CONFIG_ARCH_HAS_SYSCALL_WRAPPER
	select CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS if CONFIG_IOMMU_SUPPORT
	select CONFIG_ARCH_HAS_TICK_BROADCAST if CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
	select CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG
	select CONFIG_ARCH_INLINE_READ_LOCK if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_READ_LOCK_BH if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_READ_LOCK_IRQ if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_READ_UNLOCK if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_READ_UNLOCK_BH if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_WRITE_LOCK if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_WRITE_LOCK_BH if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_WRITE_UNLOCK if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_SPIN_TRYLOCK if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_SPIN_LOCK if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_SPIN_LOCK_BH if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_SPIN_UNLOCK if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ if !CONFIG_PREEMPT
	select CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !CONFIG_PREEMPT
	select CONFIG_ARCH_KEEP_MEMBLOCK
	select CONFIG_ARCH_USE_CMPXCHG_LOCKREF
	select CONFIG_ARCH_USE_QUEUED_RWLOCKS
	select CONFIG_ARCH_USE_QUEUED_SPINLOCKS
	select CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE
	select CONFIG_ARCH_SUPPORTS_ATOMIC_RMW
	select CONFIG_ARCH_SUPPORTS_INT128 if CONFIG_GCC_VERSION >= 50000 || CONFIG_CC_IS_CLANG
	select CONFIG_ARCH_SUPPORTS_NUMA_BALANCING
	select CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION if CONFIG_COMPAT
	select CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
	select CONFIG_ARCH_WANT_FRAME_POINTERS
	select CONFIG_ARCH_WANT_HUGE_PMD_SHARE if CONFIG_ARM64_4K_PAGES || (CONFIG_ARM64_16K_PAGES && !CONFIG_ARM64_VA_BITS_36)
	select CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL
	select CONFIG_ARM_AMBA
	select CONFIG_ARM_ARCH_TIMER
	select CONFIG_ARM_GIC
	select CONFIG_AUDIT_ARCH_COMPAT_GENERIC
	select CONFIG_ARM_GIC_V2M if CONFIG_PCI
	select CONFIG_ARM_GIC_V3
	select CONFIG_ARM_GIC_V3_ITS if CONFIG_PCI
	select CONFIG_ARM_PSCI_FW
	select CONFIG_BUILDTIME_EXTABLE_SORT
	select CONFIG_CLONE_BACKWARDS
	select CONFIG_COMMON_CLK
	select CONFIG_CPU_PM if (CONFIG_SUSPEND || CONFIG_CPU_IDLE)
	select CONFIG_CRC32
	select CONFIG_DCACHE_WORD_ACCESS
	select CONFIG_DMA_DIRECT_REMAP
	select CONFIG_EDAC_SUPPORT
	select CONFIG_FRAME_POINTER
	select CONFIG_GENERIC_ALLOCATOR
	select CONFIG_GENERIC_ARCH_TOPOLOGY
	select CONFIG_GENERIC_CLOCKEVENTS
	select CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
	select CONFIG_GENERIC_CPU_AUTOPROBE
	select CONFIG_GENERIC_CPU_VULNERABILITIES
	select CONFIG_GENERIC_EARLY_IOREMAP
	select CONFIG_GENERIC_IDLE_POLL_SETUP
	select CONFIG_GENERIC_IRQ_MULTI_HANDLER
	select CONFIG_GENERIC_IRQ_PROBE
	select CONFIG_GENERIC_IRQ_SHOW
	select CONFIG_GENERIC_IRQ_SHOW_LEVEL
	select CONFIG_GENERIC_PCI_IOMAP
	select CONFIG_GENERIC_SCHED_CLOCK
	select CONFIG_GENERIC_SMP_IDLE_THREAD
	select CONFIG_GENERIC_STRNCPY_FROM_USER
	select CONFIG_GENERIC_STRNLEN_USER
	select CONFIG_GENERIC_TIME_VSYSCALL
	select CONFIG_GENERIC_GETTIMEOFDAY
	select CONFIG_HANDLE_DOMAIN_IRQ
	select CONFIG_HARDIRQS_SW_RESEND
	select CONFIG_HAVE_PCI
	select CONFIG_HAVE_ACPI_APEI if (CONFIG_ACPI && CONFIG_EFI)
	select CONFIG_HAVE_ALIGNED_STRUCT_PAGE if CONFIG_SLUB
	select CONFIG_HAVE_ARCH_AUDITSYSCALL
	select CONFIG_HAVE_ARCH_BITREVERSE
	select CONFIG_HAVE_ARCH_HUGE_VMAP
	select CONFIG_HAVE_ARCH_JUMP_LABEL
	select CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE
	select CONFIG_HAVE_ARCH_KASAN if !(CONFIG_ARM64_16K_PAGES && CONFIG_ARM64_VA_BITS_48)
	select CONFIG_HAVE_ARCH_KASAN_SW_TAGS if CONFIG_HAVE_ARCH_KASAN
	select CONFIG_HAVE_ARCH_KGDB
	select CONFIG_HAVE_ARCH_MMAP_RND_BITS
	select CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS if CONFIG_COMPAT
	select CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
	select CONFIG_HAVE_ARCH_SECCOMP_FILTER
	select CONFIG_HAVE_ARCH_STACKLEAK
	select CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST
	select CONFIG_HAVE_ARCH_TRACEHOOK
	select CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE
	select CONFIG_HAVE_ARCH_VMAP_STACK
	select CONFIG_HAVE_ARM_SMCCC
	select CONFIG_HAVE_ASM_MODVERSIONS
	select CONFIG_HAVE_EBPF_JIT
	select CONFIG_HAVE_C_RECORDMCOUNT
	select CONFIG_HAVE_CMPXCHG_DOUBLE
	select CONFIG_HAVE_CMPXCHG_LOCAL
	select CONFIG_HAVE_CONTEXT_TRACKING
	select CONFIG_HAVE_DEBUG_BUGVERBOSE
	select CONFIG_HAVE_DEBUG_KMEMLEAK
	select CONFIG_HAVE_DMA_CONTIGUOUS
	select CONFIG_HAVE_DYNAMIC_FTRACE
	select CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
	select CONFIG_HAVE_FAST_GUP
	select CONFIG_HAVE_FTRACE_MCOUNT_RECORD
	select CONFIG_HAVE_FUNCTION_TRACER
	select CONFIG_HAVE_FUNCTION_ERROR_INJECTION
	select CONFIG_HAVE_FUNCTION_GRAPH_TRACER
	select CONFIG_HAVE_GCC_PLUGINS
	select CONFIG_HAVE_HW_BREAKPOINT if CONFIG_PERF_EVENTS
	select CONFIG_HAVE_IRQ_TIME_ACCOUNTING
	select CONFIG_HAVE_MEMBLOCK_NODE_MAP if CONFIG_NUMA
	select CONFIG_HAVE_NMI
	select CONFIG_HAVE_PATA_PLATFORM
	select CONFIG_HAVE_PERF_EVENTS
	select CONFIG_HAVE_PERF_REGS
	select CONFIG_HAVE_PERF_USER_STACK_DUMP
	select CONFIG_HAVE_REGS_AND_STACK_ACCESS_API
	select CONFIG_HAVE_FUNCTION_ARG_ACCESS_API
	select CONFIG_HAVE_RCU_TABLE_FREE
	select CONFIG_HAVE_RSEQ
	select CONFIG_HAVE_STACKPROTECTOR
	select CONFIG_HAVE_SYSCALL_TRACEPOINTS
	select CONFIG_HAVE_KPROBES
	select CONFIG_HAVE_KRETPROBES
	select CONFIG_HAVE_GENERIC_VDSO
	select CONFIG_IOMMU_DMA if CONFIG_IOMMU_SUPPORT
	select CONFIG_IRQ_DOMAIN
	select CONFIG_IRQ_FORCED_THREADING
	select CONFIG_MODULES_USE_ELF_RELA
	select CONFIG_NEED_DMA_MAP_STATE
	select CONFIG_NEED_SG_DMA_LENGTH
	select CONFIG_OF
	select CONFIG_OF_EARLY_FLATTREE
	select CONFIG_PCI_DOMAINS_GENERIC if CONFIG_PCI
	select CONFIG_PCI_ECAM if (CONFIG_ACPI && CONFIG_PCI)
	select CONFIG_PCI_SYSCALL if CONFIG_PCI
	select CONFIG_POWER_RESET
	select CONFIG_POWER_SUPPLY
	select CONFIG_REFCOUNT_FULL
	select CONFIG_SPARSE_IRQ
	select CONFIG_SWIOTLB
	select CONFIG_SYSCTL_EXCEPTION_TRACE
	select CONFIG_THREAD_INFO_IN_TASK
	help
	  CONFIG_ARM 64-bit (AArch64) Linux support.

config CONFIG_64BIT
	def_bool y

config CONFIG_MMU
	def_bool y

config CONFIG_ARM64_PAGE_SHIFT
	int
	default 16 if CONFIG_ARM64_64K_PAGES
	default 14 if CONFIG_ARM64_16K_PAGES
	default 12

config CONFIG_ARM64_CONT_SHIFT
	int
	default 5 if CONFIG_ARM64_64K_PAGES
	default 7 if CONFIG_ARM64_16K_PAGES
	default 4

config CONFIG_ARCH_MMAP_RND_BITS_MIN
       default 14 if CONFIG_ARM64_64K_PAGES
       default 16 if CONFIG_ARM64_16K_PAGES
       default 18

# max bits determined by the following formula:
#  CONFIG_VA_BITS - PAGE_SHIFT - 3
config CONFIG_ARCH_MMAP_RND_BITS_MAX
       default 19 if CONFIG_ARM64_VA_BITS=36
       default 24 if CONFIG_ARM64_VA_BITS=39
       default 27 if CONFIG_ARM64_VA_BITS=42
       default 30 if CONFIG_ARM64_VA_BITS=47
       default 29 if CONFIG_ARM64_VA_BITS=48 && CONFIG_ARM64_64K_PAGES
       default 31 if CONFIG_ARM64_VA_BITS=48 && CONFIG_ARM64_16K_PAGES
       default 33 if CONFIG_ARM64_VA_BITS=48
       default 14 if CONFIG_ARM64_64K_PAGES
       default 16 if CONFIG_ARM64_16K_PAGES
       default 18

config CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN
       default 7 if CONFIG_ARM64_64K_PAGES
       default 9 if CONFIG_ARM64_16K_PAGES
       default 11

config CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX
       default 16

config CONFIG_NO_IOPORT_MAP
	def_bool y if !CONFIG_PCI

config CONFIG_STACKTRACE_SUPPORT
	def_bool y

config CONFIG_ILLEGAL_POINTER_VALUE
	hex
	default 0xdead000000000000

config CONFIG_LOCKDEP_SUPPORT
	def_bool y

config CONFIG_TRACE_IRQFLAGS_SUPPORT
	def_bool y

config CONFIG_GENERIC_BUG
	def_bool y
	depends on CONFIG_BUG

config CONFIG_GENERIC_BUG_RELATIVE_POINTERS
	def_bool y
	depends on CONFIG_GENERIC_BUG

config CONFIG_GENERIC_HWEIGHT
	def_bool y

config CONFIG_GENERIC_CSUM
        def_bool y

config CONFIG_GENERIC_CALIBRATE_DELAY
	def_bool y

config CONFIG_ZONE_DMA32
	bool "Support DMA32 zone" if CONFIG_EXPERT
	default y

config CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG
	def_bool y

config CONFIG_SMP
	def_bool y

config CONFIG_KERNEL_MODE_NEON
	def_bool y

config CONFIG_FIX_EARLYCON_MEM
	def_bool y

config CONFIG_PGTABLE_LEVELS
	int
	default 2 if CONFIG_ARM64_16K_PAGES && CONFIG_ARM64_VA_BITS_36
	default 2 if CONFIG_ARM64_64K_PAGES && CONFIG_ARM64_VA_BITS_42
	default 3 if CONFIG_ARM64_64K_PAGES && (CONFIG_ARM64_VA_BITS_48 || CONFIG_ARM64_VA_BITS_52)
	default 3 if CONFIG_ARM64_4K_PAGES && CONFIG_ARM64_VA_BITS_39
	default 3 if CONFIG_ARM64_16K_PAGES && CONFIG_ARM64_VA_BITS_47
	default 4 if !CONFIG_ARM64_64K_PAGES && CONFIG_ARM64_VA_BITS_48

config CONFIG_ARCH_SUPPORTS_UPROBES
	def_bool y

config CONFIG_ARCH_PROC_KCORE_TEXT
	def_bool y

config CONFIG_KASAN_SHADOW_OFFSET
	hex
	depends on CONFIG_KASAN
	default 0xdfffa00000000000 if (CONFIG_ARM64_VA_BITS_48 || CONFIG_ARM64_VA_BITS_52) && !CONFIG_KASAN_SW_TAGS
	default 0xdfffd00000000000 if CONFIG_ARM64_VA_BITS_47 && !CONFIG_KASAN_SW_TAGS
	default 0xdffffe8000000000 if CONFIG_ARM64_VA_BITS_42 && !CONFIG_KASAN_SW_TAGS
	default 0xdfffffd000000000 if CONFIG_ARM64_VA_BITS_39 && !CONFIG_KASAN_SW_TAGS
	default 0xdffffffa00000000 if CONFIG_ARM64_VA_BITS_36 && !CONFIG_KASAN_SW_TAGS
	default 0xefff900000000000 if (CONFIG_ARM64_VA_BITS_48 || CONFIG_ARM64_VA_BITS_52) && CONFIG_KASAN_SW_TAGS
	default 0xefffc80000000000 if CONFIG_ARM64_VA_BITS_47 && CONFIG_KASAN_SW_TAGS
	default 0xeffffe4000000000 if CONFIG_ARM64_VA_BITS_42 && CONFIG_KASAN_SW_TAGS
	default 0xefffffc800000000 if CONFIG_ARM64_VA_BITS_39 && CONFIG_KASAN_SW_TAGS
	default 0xeffffff900000000 if CONFIG_ARM64_VA_BITS_36 && CONFIG_KASAN_SW_TAGS
	default 0xffffffffffffffff

source "arch/arm64/Kconfig.platforms"

menu "Kernel Features"

menu "ARM errata workarounds via the alternatives framework"

config CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
	bool

config CONFIG_ARM64_ERRATUM_826319
	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
	default y
	select CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
	help
	  This option adds an alternative code sequence to work around CONFIG_ARM
	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
	  AXI master interface and an L2 cache.

	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
	  and is unable to accept a certain write via this interface, it will
	  not progress on read data presented on the read data channel and the
	  system can deadlock.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config CONFIG_ARM64_ERRATUM_827319
	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
	default y
	select CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
	help
	  This option adds an alternative code sequence to work around CONFIG_ARM
	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
	  master interface and an L2 cache.

	  Under certain conditions this erratum can cause a clean line eviction
	  to occur at the same time as another transaction to the same address
	  on the AMBA 5 CHI interface, which can cause data corruption if the
	  interconnect reorders the two transactions.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config CONFIG_ARM64_ERRATUM_824069
	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
	default y
	select CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
	help
	  This option adds an alternative code sequence to work around CONFIG_ARM
	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
	  to a coherent interconnect.

	  If a Cortex-A53 processor is executing a store or prefetch for
	  write instruction at the same time as a processor in another
	  cluster is executing a cache maintenance operation to the same
	  address, then this erratum might cause a clean cache line to be
	  incorrectly marked as dirty.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this option does not necessarily enable the
	  workaround, as it depends on the alternative framework, which will
	  only patch the kernel if an affected CPU is detected.

	  If unsure, say Y.

config CONFIG_ARM64_ERRATUM_819472
	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
	default y
	select CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
	help
	  This option adds an alternative code sequence to work around CONFIG_ARM
	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
	  present when it is connected to a coherent interconnect.

	  If the processor is executing a load and store exclusive sequence at
	  the same time as a processor in another cluster is executing a cache
	  maintenance operation to the same address, then this erratum might
	  cause data corruption.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config CONFIG_ARM64_ERRATUM_832075
	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
	default y
	help
	  This option adds an alternative code sequence to work around CONFIG_ARM
	  erratum 832075 on Cortex-A57 parts up to r1p2.

	  Affected Cortex-A57 parts might deadlock when exclusive load/store
	  instructions to Write-Back memory are mixed with Device loads.

	  The workaround is to promote device loads to use Load-Acquire
	  semantics.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config CONFIG_ARM64_ERRATUM_834220
	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
	depends on CONFIG_KVM
	default y
	help
	  This option adds an alternative code sequence to work around CONFIG_ARM
	  erratum 834220 on Cortex-A57 parts up to r1p2.

	  Affected Cortex-A57 parts might report a Stage 2 translation
	  fault as the result of a Stage 1 fault for load crossing a
	  page boundary when there is a permission or device memory
	  alignment fault at Stage 1 and a translation fault at Stage 2.

	  The workaround is to verify that the Stage 1 translation
	  doesn't generate a fault before handling the Stage 2 fault.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config CONFIG_ARM64_ERRATUM_845719
	bool "Cortex-A53: 845719: a load might read incorrect data"
	depends on CONFIG_COMPAT
	default y
	help
	  This option adds an alternative code sequence to work around CONFIG_ARM
	  erratum 845719 on Cortex-A53 parts up to r0p4.

	  When running a compat (AArch32) userspace on an affected Cortex-A53
	  part, a load at EL0 from a virtual address that matches the bottom 32
	  bits of the virtual address used by a recent load at (AArch64) EL1
	  might return incorrect data.

	  The workaround is to write the contextidr_el1 register on exception
	  return to a 32-bit task.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config CONFIG_ARM64_ERRATUM_843419
	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
	default y
	select CONFIG_ARM64_MODULE_PLTS if CONFIG_MODULES
	help
	  This option links the kernel with '--fix-cortex-a53-843419' and
	  enables PLT support to replace certain ADRP instructions, which can
	  cause subsequent memory accesses to use an incorrect address on
	  Cortex-A53 parts up to r0p4.

	  If unsure, say Y.

config CONFIG_ARM64_ERRATUM_1024718
	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
	default y
	help
	  This option adds a workaround for CONFIG_ARM Cortex-A55 Erratum 1024718.

	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
	  update of the hardware dirty bit when the DBM/AP bits are updated
	  without a break-before-make. The workaround is to disable the usage
	  of hardware DBM locally on the affected cores. CPUs not affected by
	  this erratum will continue to use the feature.

	  If unsure, say Y.

config CONFIG_ARM64_ERRATUM_1418040
	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
	default y
	depends on CONFIG_COMPAT
	help
	  This option adds a workaround for CONFIG_ARM Cortex-A76/Neoverse-N1
	  errata 1188873 and 1418040.

	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
	  cause register corruption when accessing the timer registers
	  from AArch32 userspace.

	  If unsure, say Y.

config CONFIG_ARM64_ERRATUM_1165522
	bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
	default y
	help
	  This option adds a workaround for CONFIG_ARM Cortex-A76 erratum 1165522.

	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
	  corrupted TLBs by speculating an AT instruction during a guest
	  context switch.

	  If unsure, say Y.

config CONFIG_ARM64_ERRATUM_1286807
	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
	default y
	select CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
	help
	  This option adds a workaround for CONFIG_ARM Cortex-A76 erratum 1286807.

	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
	  address for a cacheable mapping of a location is being
	  accessed by a core while another core is remapping the virtual
	  address to a new physical page using the recommended
	  break-before-make sequence, then under very rare circumstances
	  TLBI+DSB completes before a read using the translation being
	  invalidated has been observed by other observers. The
	  workaround repeats the TLBI+DSB operation.

	  If unsure, say Y.

config CONFIG_ARM64_ERRATUM_1463225
	bool "Cortex-A76: Software Step might prevent interrupt recognition"
	default y
	help
	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.

	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
	  of a system call instruction (SVC) can prevent recognition of
	  subsequent interrupts when software stepping is disabled in the
	  exception handler of the system call and either kernel debugging
	  is enabled or VHE is in use.

	  Work around the erratum by triggering a dummy step exception
	  when handling a system call from a task that is being stepped
	  in a VHE configuration of the kernel.

	  If unsure, say Y.

config CONFIG_CAVIUM_ERRATUM_22375
	bool "Cavium erratum 22375, 24313"
	default y
	help
	  Enable workaround for errata 22375 and 24313.

	  This implements two gicv3-its errata workarounds for ThunderX. Both
	  with a small impact affecting only ITS table allocation.

	    erratum 22375: only alloc 8MB table size
	    erratum 24313: ignore memory access type

	  The fixes are in ITS initialization and basically ignore memory access
	  type and table size provided by the TYPER and BASER registers.

	  If unsure, say Y.

config CONFIG_CAVIUM_ERRATUM_23144
	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
	depends on CONFIG_NUMA
	default y
	help
	  ITS SYNC command hang for cross node io and collections/cpu mapping.

	  If unsure, say Y.

config CONFIG_CAVIUM_ERRATUM_23154
	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
	default y
	help
	  The gicv3 of ThunderX requires a modified version for
	  reading the IAR status to ensure data synchronization
	  (access to icc_iar1_el1 is not sync'ed before and after).

	  If unsure, say Y.

config CONFIG_CAVIUM_ERRATUM_27456
	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
	default y
	help
	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
	  instructions may cause the icache to become corrupted if it
	  contains data for a non-current ASID.  The fix is to
	  invalidate the icache when changing the mm context.

	  If unsure, say Y.

config CONFIG_CAVIUM_ERRATUM_30115
	bool "Cavium erratum 30115: Guest may disable interrupts in host"
	default y
	help
	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
	  1.2, and T83 Pass 1.0, CONFIG_KVM guest execution may disable
	  interrupts in host. Trapping both GICv3 group-0 and group-1
	  accesses sidesteps the issue.

	  If unsure, say Y.

config CONFIG_CAVIUM_TX2_ERRATUM_219
	bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
	default y
	help
	  On Cavium ThunderX2, a load, store or prefetch instruction between a
	  TTBR update and the corresponding context synchronizing operation can
	  cause a spurious Data Abort to be delivered to any hardware thread in
	  the CPU core.

	  Work around the issue by avoiding the problematic code sequence and
	  trapping CONFIG_KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
	  trap handler performs the corresponding register access, skips the
	  instruction and ensures context synchronization by virtue of the
	  exception return.

	  If unsure, say Y.

config CONFIG_QCOM_FALKOR_ERRATUM_1003
	bool "Falkor E1003: Incorrect translation due to ASID change"
	default y
	help
	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
	  then only for entries in the walk cache, since the leaf translation
	  is unchanged. Work around the erratum by invalidating the walk cache
	  entries for the trampoline before entering the kernel proper.

config CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
	bool

config CONFIG_QCOM_FALKOR_ERRATUM_1009
	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
	default y
	select CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
	help
	  On Falkor v1, the CPU may prematurely complete a DSB following a
	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
	  one more time to fix the issue.

	  If unsure, say Y.

config CONFIG_QCOM_QDF2400_ERRATUM_0065
	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
	default y
	help
	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).

	  If unsure, say Y.

config CONFIG_SOCIONEXT_SYNQUACER_PREITS
	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
	default y
	help
	  Socionext Synquacer SoCs implement a separate h/w block to generate
	  MSI doorbell writes with non-zero values for the device ID.

	  If unsure, say Y.

config CONFIG_HISILICON_ERRATUM_161600802
	bool "Hip07 161600802: Erroneous redistributor VLPI base"
	default y
	help
	  The HiSilicon Hip07 SoC uses the wrong redistributor base
	  when issued ITS commands such as VMOVP and VMAPP, and requires
	  a 128kB offset to be applied to the target address in this commands.

	  If unsure, say Y.

config CONFIG_QCOM_FALKOR_ERRATUM_E1041
	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
	default y
	help
	  Falkor CPU may speculatively fetch instructions from an improper
	  memory location when CONFIG_MMU translation is changed from SCTLR_ELn[CONFIG_M]=1
	  to SCTLR_ELn[CONFIG_M]=0. Prefix an ISB instruction to fix the problem.

	  If unsure, say Y.

config CONFIG_FUJITSU_ERRATUM_010001
	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
	default y
	help
	  This option adds a workaround for Fujitsu-A64FX erratum CONFIG_E#010001.
	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
	  accesses may cause undefined fault (Data abort, DFSC=0b111111).
	  This fault occurs under a specific hardware condition when a
	  load/store instruction performs an address translation using:
	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.

	  The workaround is to ensure these bits are clear in TCR_ELx.
	  The workaround only affects the Fujitsu-A64FX.

	  If unsure, say Y.

endmenu


choice
	prompt "Page size"
	default CONFIG_ARM64_4K_PAGES
	help
	  Page size (translation granule) configuration.

config CONFIG_ARM64_4K_PAGES
	bool "4KB"
	help
	  This feature enables 4KB pages support.

config CONFIG_ARM64_16K_PAGES
	bool "16KB"
	help
	  The system will use 16KB pages support. AArch32 emulation
	  requires applications compiled with 16K (or a multiple of 16K)
	  aligned segments.

config CONFIG_ARM64_64K_PAGES
	bool "64KB"
	help
	  This feature enables 64KB pages support (4KB by default)
	  allowing only two levels of page tables and faster TLB
	  look-up. AArch32 emulation requires applications compiled
	  with 64K aligned segments.

endchoice

choice
	prompt "Virtual address space size"
	default CONFIG_ARM64_VA_BITS_39 if CONFIG_ARM64_4K_PAGES
	default CONFIG_ARM64_VA_BITS_47 if CONFIG_ARM64_16K_PAGES
	default CONFIG_ARM64_VA_BITS_42 if CONFIG_ARM64_64K_PAGES
	help
	  Allows choosing one of multiple possible virtual address
	  space sizes. The level of translation table is determined by
	  a combination of page size and virtual address space size.

config CONFIG_ARM64_VA_BITS_36
	bool "36-bit" if CONFIG_EXPERT
	depends on CONFIG_ARM64_16K_PAGES

config CONFIG_ARM64_VA_BITS_39
	bool "39-bit"
	depends on CONFIG_ARM64_4K_PAGES

config CONFIG_ARM64_VA_BITS_42
	bool "42-bit"
	depends on CONFIG_ARM64_64K_PAGES

config CONFIG_ARM64_VA_BITS_47
	bool "47-bit"
	depends on CONFIG_ARM64_16K_PAGES

config CONFIG_ARM64_VA_BITS_48
	bool "48-bit"

config CONFIG_ARM64_VA_BITS_52
	bool "52-bit"
	depends on CONFIG_ARM64_64K_PAGES && (CONFIG_ARM64_PAN || !CONFIG_ARM64_SW_TTBR0_PAN)
	help
	  Enable 52-bit virtual addressing for userspace when explicitly
	  requested via a hint to mmap(). The kernel will also use 52-bit
	  virtual addresses for its own mappings (provided HW support for
	  this feature is available, otherwise it reverts to 48-bit).

	  NOTE: Enabling 52-bit virtual addressing in conjunction with
	  ARMv8.3 Pointer Authentication will result in the PAC being
	  reduced from 7 bits to 3 bits, which may have a significant
	  impact on its susceptibility to brute-force attacks.

	  If unsure, select 48-bit virtual addressing instead.

endchoice

config CONFIG_ARM64_FORCE_52BIT
	bool "Force 52-bit virtual addresses for userspace"
	depends on CONFIG_ARM64_VA_BITS_52 && CONFIG_EXPERT
	help
	  For systems with 52-bit userspace VAs enabled, the kernel will attempt
	  to maintain compatibility with older software by providing 48-bit VAs
	  unless a hint is supplied to mmap.

	  This configuration option disables the 48-bit compatibility logic, and
	  forces all userspace addresses to be 52-bit on HW that supports it. One
	  should only enable this configuration option for stress testing userspace
	  memory management code. If unsure say N here.

config CONFIG_ARM64_VA_BITS
	int
	default 36 if CONFIG_ARM64_VA_BITS_36
	default 39 if CONFIG_ARM64_VA_BITS_39
	default 42 if CONFIG_ARM64_VA_BITS_42
	default 47 if CONFIG_ARM64_VA_BITS_47
	default 48 if CONFIG_ARM64_VA_BITS_48
	default 52 if CONFIG_ARM64_VA_BITS_52

choice
	prompt "Physical address space size"
	default CONFIG_ARM64_PA_BITS_48
	help
	  Choose the maximum physical address range that the kernel will
	  support.

config CONFIG_ARM64_PA_BITS_48
	bool "48-bit"

config CONFIG_ARM64_PA_BITS_52
	bool "52-bit (ARMv8.2)"
	depends on CONFIG_ARM64_64K_PAGES
	depends on CONFIG_ARM64_PAN || !CONFIG_ARM64_SW_TTBR0_PAN
	help
	  Enable support for a 52-bit physical address space, introduced as
	  part of the ARMv8.2-LPA extension.

	  With this enabled, the kernel will also continue to work on CPUs that
	  do not support ARMv8.2-LPA, but with some added memory overhead (and
	  minor performance overhead).

endchoice

config CONFIG_ARM64_PA_BITS
	int
	default 48 if CONFIG_ARM64_PA_BITS_48
	default 52 if CONFIG_ARM64_PA_BITS_52

config CONFIG_CPU_BIG_ENDIAN
       bool "Build big-endian kernel"
       help
         Say Y if you plan on running a kernel in big-endian mode.

config CONFIG_SCHED_MC
	bool "Multi-core scheduler support"
	help
	  Multi-core scheduler support improves the CPU scheduler's decision
	  making when dealing with multi-core CPU chips at a cost of slightly
	  increased overhead in some places. If unsure say N here.

config CONFIG_SCHED_SMT
	bool "SMT scheduler support"
	help
	  Improves the CPU scheduler's decision making when dealing with
	  MultiThreading at a cost of slightly increased overhead in some
	  places. If unsure say N here.

config CONFIG_NR_CPUS
	int "Maximum number of CPUs (2-4096)"
	range 2 4096
	default "256"

config CONFIG_HOTPLUG_CPU
	bool "Support for hot-pluggable CPUs"
	select CONFIG_GENERIC_IRQ_MIGRATION
	help
	  Say Y here to experiment with turning CPUs off and on.  CPUs
	  can be controlled through /sys/devices/system/cpu.

# Common CONFIG_NUMA Features
config CONFIG_NUMA
	bool "Numa Memory Allocation and Scheduler Support"
	select CONFIG_ACPI_NUMA if CONFIG_ACPI
	select CONFIG_OF_NUMA
	help
	  Enable CONFIG_NUMA (Non Uniform Memory Access) support.

	  The kernel will try to allocate memory used by a CPU on the
	  local memory of the CPU and add some more
	  CONFIG_NUMA awareness to the kernel.

config CONFIG_NODES_SHIFT
	int "Maximum NUMA Nodes (as a power of 2)"
	range 1 10
	default "2"
	depends on CONFIG_NEED_MULTIPLE_NODES
	help
	  Specify the maximum number of CONFIG_NUMA Nodes available on the target
	  system.  Increases memory reserved to accommodate various tables.

config CONFIG_USE_PERCPU_NUMA_NODE_ID
	def_bool y
	depends on CONFIG_NUMA

config CONFIG_HAVE_SETUP_PER_CPU_AREA
	def_bool y
	depends on CONFIG_NUMA

config CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK
	def_bool y
	depends on CONFIG_NUMA

config CONFIG_HOLES_IN_ZONE
	def_bool y

source "kernel/Kconfig.hz"

config CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC
	def_bool y

config CONFIG_ARCH_SPARSEMEM_ENABLE
	def_bool y
	select CONFIG_SPARSEMEM_VMEMMAP_ENABLE

config CONFIG_ARCH_SPARSEMEM_DEFAULT
	def_bool CONFIG_ARCH_SPARSEMEM_ENABLE

config CONFIG_ARCH_SELECT_MEMORY_MODEL
	def_bool CONFIG_ARCH_SPARSEMEM_ENABLE

config CONFIG_ARCH_FLATMEM_ENABLE
	def_bool !CONFIG_NUMA

config CONFIG_HAVE_ARCH_PFN_VALID
	def_bool y

config CONFIG_HW_PERF_EVENTS
	def_bool y
	depends on CONFIG_ARM_PMU

config CONFIG_SYS_SUPPORTS_HUGETLBFS
	def_bool y

config CONFIG_ARCH_WANT_HUGE_PMD_SHARE

config CONFIG_ARCH_HAS_CACHE_LINE_SIZE
	def_bool y

config CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK
	def_bool y if CONFIG_PGTABLE_LEVELS > 2

config CONFIG_SECCOMP
	bool "Enable seccomp to safely compute untrusted bytecode"
	---help---
	  This kernel feature is useful for number crunching applications
	  that may need to compute untrusted bytecode during their
	  execution. By using pipes or other transports made available to
	  the process as file descriptors supporting the read/write
	  syscalls, it's possible to isolate those applications in
	  their own address space using seccomp. Once seccomp is
	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
	  and the task is only allowed to execute a few safe syscalls
	  defined by each seccomp mode.

config CONFIG_PARAVIRT
	bool "Enable paravirtualization code"
	help
	  This changes the kernel so it can modify itself when it is run
	  under a hypervisor, potentially improving performance significantly
	  over full virtualization.

config CONFIG_PARAVIRT_TIME_ACCOUNTING
	bool "Paravirtual steal time accounting"
	select CONFIG_PARAVIRT
	help
	  Select this option to enable fine granularity task steal time
	  accounting. Time spent executing other tasks in parallel with
	  the current vCPU is discounted from the vCPU power. To account for
	  that, there can be a small performance impact.

	  If in doubt, say N here.

config CONFIG_KEXEC
	depends on CONFIG_PM_SLEEP_SMP
	select CONFIG_KEXEC_CORE
	bool "kexec system call"
	---help---
	  kexec is a system call that implements the ability to shutdown your
	  current kernel, and to start another kernel.  It is like a reboot
	  but it is independent of the system firmware.   And like a reboot
	  you can start any kernel with it, not just Linux.

config CONFIG_KEXEC_FILE
	bool "kexec file based system call"
	select CONFIG_KEXEC_CORE
	help
	  This is new version of kexec system call. This system call is
	  file based and takes file descriptors as system call argument
	  for kernel and initramfs as opposed to list of segments as
	  accepted by previous system call.

config CONFIG_KEXEC_SIG
	bool "Verify kernel signature during kexec_file_load() syscall"
	depends on CONFIG_KEXEC_FILE
	help
	  Select this option to verify a signature with loaded kernel
	  image. If configured, any attempt of loading a image without
	  valid signature will fail.

	  In addition to that option, you need to enable signature
	  verification for the corresponding kernel image type being
	  loaded in order for this to work.

config CONFIG_KEXEC_IMAGE_VERIFY_SIG
	bool "Enable Image signature verification support"
	default y
	depends on CONFIG_KEXEC_SIG
	depends on CONFIG_EFI && CONFIG_SIGNED_PE_FILE_VERIFICATION
	help
	  Enable Image signature verification support.

comment "Support for PE file signature verification disabled"
	depends on CONFIG_KEXEC_SIG
	depends on !CONFIG_EFI || !CONFIG_SIGNED_PE_FILE_VERIFICATION

config CONFIG_CRASH_DUMP
	bool "Build kdump crash kernel"
	help
	  Generate crash dump after being started by kexec. This should
	  be normally only set in special crash dump kernels which are
	  loaded in the main kernel with kexec-tools into a specially
	  reserved region and then later executed after a crash by
	  kdump/kexec.

	  For more details see Documentation/admin-guide/kdump/kdump.rst

config CONFIG_XEN_DOM0
	def_bool y
	depends on CONFIG_XEN

config CONFIG_XEN
	bool "Xen guest support on ARM64"
	depends on CONFIG_ARM64 && CONFIG_OF
	select CONFIG_SWIOTLB_XEN
	select CONFIG_PARAVIRT
	help
	  Say Y if you want to run Linux in a Virtual Machine on Xen on CONFIG_ARM64.

config CONFIG_FORCE_MAX_ZONEORDER
	int
	default "14" if (CONFIG_ARM64_64K_PAGES && CONFIG_TRANSPARENT_HUGEPAGE)
	default "12" if (CONFIG_ARM64_16K_PAGES && CONFIG_TRANSPARENT_HUGEPAGE)
	default "11"
	help
	  The kernel memory allocator divides physically contiguous memory
	  blocks into "zones", where each zone is a power of two number of
	  pages.  This option selects the largest power of two that the kernel
	  keeps in the memory allocator.  If you need to allocate very large
	  blocks of physically contiguous memory, then you may need to
	  increase this value.

	  This config option is actually maximum order plus one. For example,
	  a value of 11 means that the largest free memory block is 2^10 pages.

	  We make sure that we can allocate upto a HugePage size for each configuration.
	  Hence we have :
		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2

	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
	  4M allocations matching the default size used by generic code.

config CONFIG_UNMAP_KERNEL_AT_EL0
	bool "Unmap kernel when running in userspace (aka \"KAISER\")" if CONFIG_EXPERT
	default y
	help
	  Speculation attacks against some high-performance processors can
	  be used to bypass CONFIG_MMU permission checks and leak kernel data to
	  userspace. This can be defended against by unmapping the kernel
	  when running in userspace, mapping it back in on exception entry
	  via a trampoline page in the vector table.

	  If unsure, say Y.

config CONFIG_HARDEN_BRANCH_PREDICTOR
	bool "Harden the branch predictor against aliasing attacks" if CONFIG_EXPERT
	default y
	help
	  Speculation attacks against some high-performance processors rely on
	  being able to manipulate the branch predictor for a victim context by
	  executing aliasing branches in the attacker context.  Such attacks
	  can be partially mitigated against by clearing internal branch
	  predictor state and limiting the prediction logic in some situations.

	  This config option will take CPU-specific actions to harden the
	  branch predictor against aliasing attacks and may rely on specific
	  instruction sequences or control bits being set by the system
	  firmware.

	  If unsure, say Y.

config CONFIG_HARDEN_EL2_VECTORS
	bool "Harden EL2 vector mapping against system register leak" if CONFIG_EXPERT
	default y
	help
	  Speculation attacks against some high-performance processors can
	  be used to leak privileged information such as the vector base
	  register, resulting in a potential defeat of the EL2 layout
	  randomization.

	  This config option will map the vectors to a fixed location,
	  independent of the EL2 code mapping, so that revealing VBAR_EL2
	  to an attacker does not give away any extra information. This
	  only gets enabled on affected CPUs.

	  If unsure, say Y.

config CONFIG_ARM64_SSBD
	bool "Speculative Store Bypass Disable" if CONFIG_EXPERT
	default y
	help
	  This enables mitigation of the bypassing of previous stores
	  by speculative loads.

	  If unsure, say Y.

config CONFIG_RODATA_FULL_DEFAULT_ENABLED
	bool "Apply r/o permissions of VM areas also to their linear aliases"
	default y
	help
	  Apply read-only attributes of VM areas to the linear alias of
	  the backing pages as well. This prevents code or read-only data
	  from being modified (inadvertently or intentionally) via another
	  mapping of the same memory page. This additional enhancement can
	  be turned off at runtime by passing rodata=[off|on] (and turned on
	  with rodata=full if this option is set to 'n')

	  This requires the linear region to be mapped down to pages,
	  which may adversely affect performance in some cases.

config CONFIG_ARM64_SW_TTBR0_PAN
	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
	help
	  Enabling this option prevents the kernel from accessing
	  user-space memory directly by pointing TTBR0_EL1 to a reserved
	  zeroed area and reserved ASID. The user access routines
	  restore the valid TTBR0_EL1 temporarily.

config CONFIG_ARM64_TAGGED_ADDR_ABI
	bool "Enable the tagged user addresses syscall ABI"
	default y
	help
	  When this option is enabled, user applications can opt in to a
	  relaxed ABI via prctl() allowing tagged addresses to be passed
	  to system calls as pointer arguments. For details, see
	  Documentation/arm64/tagged-address-abi.rst.

menuconfig CONFIG_COMPAT
	bool "Kernel support for 32-bit EL0"
	depends on CONFIG_ARM64_4K_PAGES || CONFIG_EXPERT
	select CONFIG_COMPAT_BINFMT_ELF if CONFIG_BINFMT_ELF
	select CONFIG_HAVE_UID16
	select CONFIG_OLD_SIGSUSPEND3
	select CONFIG_COMPAT_OLD_SIGACTION
	help
	  This option enables support for a 32-bit EL0 running under a 64-bit
	  kernel at EL1. AArch32-specific components such as system calls,
	  the user helper functions, CONFIG_VFP support and the ptrace interface are
	  handled appropriately by the kernel.

	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
	  that you will only be able to execute AArch32 binaries that were compiled
	  with page size aligned segments.

	  If you want to execute 32-bit userspace applications, say Y.

if CONFIG_COMPAT

config CONFIG_KUSER_HELPERS
	bool "Enable kuser helpers page for 32-bit applications"
	default y
	help
	  Warning: disabling this option may break 32-bit user programs.

	  Provide kuser helpers to compat tasks. The kernel provides
	  helper code to userspace in read only form at a fixed location
	  to allow userspace to be independent of the CPU type fitted to
	  the system. This permits binaries to be run on ARMv4 through
	  to ARMv8 without modification.

	  See Documentation/arm/kernel_user_helpers.rst for details.

	  However, the fixed address nature of these helpers can be used
	  by ROP (return orientated programming) authors when creating
	  exploits.

	  If all of the binaries and libraries which run on your platform
	  are built specifically for your platform, and make no use of
	  these helpers, then you can turn this option off to hinder
	  such exploits. However, in that case, if a binary or library
	  relying on those helpers is run, it will not function correctly.

	  Say N here only if you are absolutely certain that you do not
	  need these helpers; otherwise, the safe option is to say Y.

config CONFIG_COMPAT_VDSO
	bool "Enable vDSO for 32-bit applications"
	depends on !CONFIG_CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
	select CONFIG_GENERIC_COMPAT_VDSO
	default y
	help
	  Place in the process address space of 32-bit applications an
	  ELF shared object providing fast implementations of gettimeofday
	  and clock_gettime.

	  You must have a 32-bit build of glibc 2.22 or later for programs
	  to seamlessly take advantage of this.

menuconfig CONFIG_ARMV8_DEPRECATED
	bool "Emulate deprecated/obsolete ARMv8 instructions"
	depends on CONFIG_SYSCTL
	help
	  Legacy software support may require certain instructions
	  that have been deprecated or obsoleted in the architecture.

	  Enable this config to enable selective emulation of these
	  features.

	  If unsure, say Y

if CONFIG_ARMV8_DEPRECATED

config CONFIG_SWP_EMULATION
	bool "Emulate SWP/SWPB instructions"
	help
	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
	  they are always undefined. Say Y here to enable software
	  emulation of these instructions for userspace using LDXR/STXR.

	  In some older versions of glibc [<=2.8] SWP is used during futex
	  trylock() operations with the assumption that the code will not
	  be preempted. This invalid assumption may be more likely to fail
	  with SWP emulation enabled, leading to deadlock of the user
	  application.

	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
	  on an external transaction monitoring block called a global
	  monitor to maintain update atomicity. If your system does not
	  implement a global monitor, this option can cause programs that
	  perform SWP operations to uncached memory to deadlock.

	  If unsure, say Y

config CONFIG_CP15_BARRIER_EMULATION
	bool "Emulate CP15 Barrier instructions"
	help
	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
	  strongly recommended to use the ISB, DSB, and DMB
	  instructions instead.

	  Say Y here to enable software emulation of these
	  instructions for AArch32 userspace code. When this option is
	  enabled, CP15 barrier usage is traced which can help
	  identify software that needs updating.

	  If unsure, say Y

config CONFIG_SETEND_EMULATION
	bool "Emulate SETEND instruction"
	help
	  The SETEND instruction alters the data-endianness of the
	  AArch32 EL0, and is deprecated in ARMv8.

	  Say Y here to enable software emulation of the instruction
	  for AArch32 userspace code.

	  Note: All the cpus on the system must have mixed endian support at EL0
	  for this feature to be enabled. If a new CPU - which doesn't support mixed
	  endian - is hotplugged in after this feature has been enabled, there could
	  be unexpected results in the applications.

	  If unsure, say Y
endif

endif

menu "ARMv8.1 architectural features"

config CONFIG_ARM64_HW_AFDBM
	bool "Support for hardware updates of the Access and Dirty page flags"
	default y
	help
	  The ARMv8.1 architecture extensions introduce support for
	  hardware updates of the access and dirty information in page
	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
	  capable processors, accesses to pages with PTE_AF cleared will
	  set this bit instead of raising an access flag fault.
	  Similarly, writes to read-only pages with the DBM bit set will
	  clear the read-only bit (AP[2]) instead of raising a
	  permission fault.

	  Kernels built with this configuration option enabled continue
	  to work on pre-ARMv8.1 hardware and the performance impact is
	  minimal. If unsure, say Y.

config CONFIG_ARM64_PAN
	bool "Enable support for Privileged Access Never (PAN)"
	default y
	help
	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
	 prevents the kernel or hypervisor from accessing user-space (EL0)
	 memory directly.

	 Choosing this option will cause any unprotected (not using
	 copy_to_user et al) memory access to fail with a permission fault.

	 The feature is detected at runtime, and will remain as a 'nop'
	 instruction if the cpu does not implement the feature.

config CONFIG_ARM64_LSE_ATOMICS
	bool "Atomic instructions"
	depends on CONFIG_JUMP_LABEL
	default y
	help
	  As part of the Large System Extensions, ARMv8.1 introduces new
	  atomic instructions that are designed specifically to scale in
	  very large systems.

	  Say Y here to make use of these instructions for the in-kernel
	  atomic routines. This incurs a small overhead on CPUs that do
	  not support these instructions and requires the kernel to be
	  built with binutils >= 2.25 in order for the new instructions
	  to be used.

config CONFIG_ARM64_VHE
	bool "Enable support for Virtualization Host Extensions (VHE)"
	default y
	help
	  Virtualization Host Extensions (VHE) allow the kernel to run
	  directly at EL2 (instead of EL1) on processors that support
	  it. This leads to better performance for CONFIG_KVM, as they reduce
	  the cost of the world switch.

	  Selecting this option allows the VHE feature to be detected
	  at runtime, and does not affect processors that do not
	  implement this feature.

endmenu

menu "ARMv8.2 architectural features"

config CONFIG_ARM64_UAO
	bool "Enable support for User Access Override (UAO)"
	default y
	help
	  User Access Override (UAO; part of the ARMv8.2 Extensions)
	  causes the 'unprivileged' variant of the load/store instructions to
	  be overridden to be privileged.

	  This option changes get_user() and friends to use the 'unprivileged'
	  variant of the load/store instructions. This ensures that user-space
	  really did have access to the supplied memory. When addr_limit is
	  set to kernel memory the UAO bit will be set, allowing privileged
	  access to kernel memory.

	  Choosing this option will cause copy_to_user() et al to use user-space
	  memory permissions.

	  The feature is detected at runtime, the kernel will use the
	  regular load/store instructions if the cpu does not implement the
	  feature.

config CONFIG_ARM64_PMEM
	bool "Enable support for persistent memory"
	select CONFIG_ARCH_HAS_PMEM_API
	select CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE
	help
	  Say Y to enable support for the persistent memory API based on the
	  ARMv8.2 DCPoP feature.

	  The feature is detected at runtime, and the kernel will use DC CVAC
	  operations if DC CVAP is not supported (following the behaviour of
	  DC CVAP itself if the system does not define a point of persistence).

config CONFIG_ARM64_RAS_EXTN
	bool "Enable support for RAS CPU Extensions"
	default y
	help
	  CPUs that support the Reliability, Availability and Serviceability
	  (CONFIG_RAS) Extensions, part of ARMv8.2 are able to track faults and
	  errors, classify them and report them to software.

	  On CPUs with these extensions system software can use additional
	  barriers to determine if faults are pending and read the
	  classification from a new set of registers.

	  Selecting this feature will allow the kernel to use these barriers
	  and access the new registers if the system supports the extension.
	  Platform CONFIG_RAS features may additionally depend on firmware support.

config CONFIG_ARM64_CNP
	bool "Enable support for Common Not Private (CNP) translations"
	default y
	depends on CONFIG_ARM64_PAN || !CONFIG_ARM64_SW_TTBR0_PAN
	help
	  Common Not Private (CNP) allows translation table entries to
	  be shared between different PEs in the same inner shareable
	  domain, so the hardware can use this fact to optimise the
	  caching of such entries in the TLB.

	  Selecting this option allows the CNP feature to be detected
	  at runtime, and does not affect PEs that do not implement
	  this feature.

endmenu

menu "ARMv8.3 architectural features"

config CONFIG_ARM64_PTR_AUTH
	bool "Enable support for pointer authentication"
	default y
	depends on !CONFIG_KVM || CONFIG_ARM64_VHE
	help
	  Pointer authentication (part of the ARMv8.3 Extensions) provides
	  instructions for signing and authenticating pointers against secret
	  keys, which can be used to mitigate Return Oriented Programming (ROP)
	  and other attacks.

	  This option enables these instructions at EL0 (i.e. for userspace).

	  Choosing this option will cause the kernel to initialise secret keys
	  for each process at exec() time, with these keys being
	  context-switched along with the process.

	  The feature is detected at runtime. If the feature is not present in
	  hardware it will not be advertised to userspace/CONFIG_KVM guest nor will it
	  be enabled. However, CONFIG_KVM guest also require VHE mode and hence
	  CONFIG_ARM64_VHE=y option to use this feature.

endmenu

config CONFIG_ARM64_SVE
	bool "ARM Scalable Vector Extension support"
	default y
	depends on !CONFIG_KVM || CONFIG_ARM64_VHE
	help
	  The Scalable Vector Extension (SVE) is an extension to the AArch64
	  execution state which complements and extends the SIMD functionality
	  of the base architecture to support much larger vectors and to enable
	  additional vectorisation opportunities.

	  To enable use of this extension on CPUs that implement it, say Y.

	  On CPUs that support the SVE2 extensions, this option will enable
	  those too.

	  Note that for architectural reasons, firmware _must_ implement SVE
	  support when running on SVE capable hardware.  The required support
	  is present in:

	    * version 1.5 and later of the CONFIG_ARM Trusted Firmware
	    * the AArch64 boot wrapper since commit 5e1261e08abf
	      ("bootwrapper: SVE: Enable SVE for EL2 and below").

	  For other firmware implementations, consult the firmware documentation
	  or vendor.

	  If you need the kernel to boot on SVE-capable hardware with broken
	  firmware, you may need to say N here until you get your firmware
	  fixed.  Otherwise, you may experience firmware panics or lockups when
	  booting the kernel.  If unsure and you are not observing these
	  symptoms, you should assume that it is safe to say Y.

	  CPUs that support SVE are architecturally required to support the
	  Virtualization Host Extensions (VHE), so the kernel makes no
	  provision for supporting SVE alongside CONFIG_KVM without VHE enabled.
	  Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
	  CONFIG_KVM in the same kernel image.

config CONFIG_ARM64_MODULE_PLTS
	bool "Use PLTs to allow module memory to spill over into vmalloc area"
	depends on CONFIG_MODULES
	select CONFIG_HAVE_MOD_ARCH_SPECIFIC
	help
	  Allocate PLTs when loading modules so that jumps and calls whose
	  targets are too far away for their relative offsets to be encoded
	  in the instructions themselves can be bounced via veneers in the
	  module's PLT. This allows modules to be allocated in the generic
	  vmalloc area after the dedicated module memory area has been
	  exhausted.

	  When running with address space randomization (KASLR), the module
	  region itself may be too far away for ordinary relative jumps and
	  calls, and so in that case, module PLTs are required and cannot be
	  disabled.

	  Specific errata workaround(s) might also force module PLTs to be
	  enabled (CONFIG_ARM64_ERRATUM_843419).

config CONFIG_ARM64_PSEUDO_NMI
	bool "Support for NMI-like interrupts"
	select CONFIG_ARM_GIC_V3
	help
	  Adds support for mimicking Non-Maskable Interrupts through the use of
	  GIC interrupt priority. This support requires version 3 or later of
	  CONFIG_ARM GIC.

	  This high priority configuration for interrupts needs to be
	  explicitly enabled by setting the kernel parameter
	  "irqchip.gicv3_pseudo_nmi" to 1.

	  If unsure, say N

if CONFIG_ARM64_PSEUDO_NMI
config CONFIG_ARM64_DEBUG_PRIORITY_MASKING
	bool "Debug interrupt priority masking"
	help
	  This adds runtime checks to functions enabling/disabling
	  interrupts when using priority masking. The additional checks verify
	  the validity of ICC_PMR_EL1 when calling concerned functions.

	  If unsure, say N
endif

config CONFIG_RELOCATABLE
	bool
	select CONFIG_ARCH_HAS_RELR
	help
	  This builds the kernel as a Position Independent Executable (PIE),
	  which retains all relocation metadata required to relocate the
	  kernel binary at runtime to a different virtual address than the
	  address it was linked at.
	  Since AArch64 uses the RELA relocation format, this requires a
	  relocation pass at runtime even if the kernel is loaded at the
	  same address it was linked at.

config CONFIG_RANDOMIZE_BASE
	bool "Randomize the address of the kernel image"
	select CONFIG_ARM64_MODULE_PLTS if CONFIG_MODULES
	select CONFIG_RELOCATABLE
	help
	  Randomizes the virtual address at which the kernel image is
	  loaded, as a security feature that deters exploit attempts
	  relying on knowledge of the location of kernel internals.

	  It is the bootloader's job to provide entropy, by passing a
	  random u64 value in /chosen/kaslr-seed at kernel entry.

	  When booting via the UEFI stub, it will invoke the firmware's
	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
	  to the kernel proper. In addition, it will randomise the physical
	  location of the kernel Image as well.

	  If unsure, say N.

config CONFIG_RANDOMIZE_MODULE_REGION_FULL
	bool "Randomize the module region over a 4 GB range"
	depends on CONFIG_RANDOMIZE_BASE
	default y
	help
	  Randomizes the location of the module region inside a 4 GB window
	  covering the core kernel. This way, it is less likely for modules
	  to leak information about the location of core kernel data structures
	  but it does imply that function calls between modules and the core
	  kernel will need to be resolved via veneers in the module PLT.

	  When this option is not set, the module region will be randomized over
	  a limited range that contains the [_stext, _etext] interval of the
	  core kernel, so branch relocations are always in range.

config CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG
	def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)

config CONFIG_STACKPROTECTOR_PER_TASK
	def_bool y
	depends on CONFIG_STACKPROTECTOR && CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG

endmenu

menu "Boot options"

config CONFIG_ARM64_ACPI_PARKING_PROTOCOL
	bool "Enable support for the ARM64 ACPI parking protocol"
	depends on CONFIG_ACPI
	help
	  Enable support for the CONFIG_ARM64 CONFIG_ACPI parking protocol. If disabled
	  the kernel will not allow booting through the CONFIG_ARM64 CONFIG_ACPI parking
	  protocol even if the corresponding data is present in the CONFIG_ACPI
	  MADT table.

config CONFIG_CMDLINE
	string "Default kernel command string"
	default ""
	help
	  Provide a set of default command-line options at build time by
	  entering them here. As a minimum, you should specify the the
	  root device (e.g. root=/dev/nfs).

config CONFIG_CMDLINE_FORCE
	bool "Always use the default kernel command string"
	help
	  Always use the default kernel command string, even if the boot
	  loader passes other arguments to the kernel.
	  This is useful if you cannot or don't want to change the
	  command-line options your boot loader passes to the kernel.

config CONFIG_EFI_STUB
	bool

config CONFIG_EFI
	bool "UEFI runtime support"
	depends on CONFIG_OF && !CONFIG_CPU_BIG_ENDIAN
	depends on CONFIG_KERNEL_MODE_NEON
	select CONFIG_ARCH_SUPPORTS_ACPI
	select CONFIG_LIBFDT
	select CONFIG_UCS2_STRING
	select CONFIG_EFI_PARAMS_FROM_FDT
	select CONFIG_EFI_RUNTIME_WRAPPERS
	select CONFIG_EFI_STUB
	select CONFIG_EFI_ARMSTUB
	default y
	help
	  This option provides support for runtime services provided
	  by UEFI firmware (such as non-volatile variables, realtime
          clock, and platform reset). CONFIG_A UEFI stub is also provided to
	  allow the kernel to be booted as an CONFIG_EFI application. This
	  is only useful on systems that have UEFI firmware.

config CONFIG_DMI
	bool "Enable support for SMBIOS (DMI) tables"
	depends on CONFIG_EFI
	default y
	help
	  This enables SMBIOS/CONFIG_DMI feature for systems.

	  This option is only useful on systems that have UEFI firmware.
	  However, even with this option, the resultant kernel should
	  continue to boot on existing non-UEFI platforms.

endmenu

config CONFIG_SYSVIPC_COMPAT
	def_bool y
	depends on CONFIG_COMPAT && CONFIG_SYSVIPC

config CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION
	def_bool y
	depends on CONFIG_HUGETLB_PAGE && CONFIG_MIGRATION

menu "Power management options"

source "kernel/power/Kconfig"

config CONFIG_ARCH_HIBERNATION_POSSIBLE
	def_bool y
	depends on CONFIG_CPU_PM

config CONFIG_ARCH_HIBERNATION_HEADER
	def_bool y
	depends on CONFIG_HIBERNATION

config CONFIG_ARCH_SUSPEND_POSSIBLE
	def_bool y

endmenu

menu "CPU Power Management"

source "drivers/cpuidle/Kconfig"

source "drivers/cpufreq/Kconfig"

endmenu

source "drivers/firmware/Kconfig"

source "drivers/acpi/Kconfig"

source "arch/arm64/kvm/Kconfig"

if CONFIG_CRYPTO
source "arch/arm64/crypto/Kconfig"
endif