/*
 * P1025 RDB Device Tree Source (32-bit address map)
 *
 * Copyright 2011 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/include/ "p1021si-pre.dtsi"
/ {
	model = "fsl,P1025RDB";
	compatible = "fsl,P1025RDB";

	memory {
		device_type = "memory";
	};

	lbc: localbus@ffe05000 {
		reg = <0 0xffe05000 0 0x1000>;

		/* NOR, NAND Flashes */
		ranges = <0x0 0x0 0x0 0xef000000 0x01000000
			  0x1 0x0 0x0 0xff800000 0x00040000>;
	};

	soc: soc@ffe00000 {
		ranges = <0x0 0x0 0xffe00000 0x100000>;
	};

	pci0: pcie@ffe09000 {
		ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
		reg = <0 0xffe09000 0 0x1000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xe0000000
				  0x2000000 0x0 0xe0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	pci1: pcie@ffe0a000 {
		reg = <0 0xffe0a000 0 0x1000>;
		ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xe0000000
				  0x2000000 0x0 0xe0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	qe: qe@ffe80000 {
		ranges = <0x0 0x0 0xffe80000 0x40000>;
		reg = <0 0xffe80000 0 0x480>;
		brg-frequency = <0>;
		bus-frequency = <0>;
		status = "disabled"; /* no firmware loaded */

		enet3: ucc@2000 {
			device_type = "network";
			compatible = "ucc_geth";
			rx-clock-name = "clk12";
			tx-clock-name = "clk9";
			pio-handle = <&pio1>;
			phy-handle = <&qe_phy0>;
			phy-connection-type = "mii";
		};

		mdio@2120 {
			qe_phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
				interrupts = <4 1 0 0>;
				reg = <0x6>;
			};
			qe_phy1: ethernet-phy@3 {
				interrupt-parent = <&mpic>;
				interrupts = <5 1 0 0>;
				reg = <0x3>;
			};
			tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		enet4: ucc@2400 {
			device_type = "network";
			compatible = "ucc_geth";
			rx-clock-name = "none";
			tx-clock-name = "clk13";
			pio-handle = <&pio2>;
			phy-handle = <&qe_phy1>;
			phy-connection-type = "rmii";
		};
	};
};

/include/ "p1025rdb.dtsi"
/include/ "p1021si-post.dtsi"