# SPDX-License-Identifier: GPL-2.0-only
#
# DMA engine configuration
#
menuconfig [31mCONFIG_DMADEVICES[0m
bool "DMA Engine support"
depends on [31mCONFIG_HAS_DMA[0m
help
DMA engines can do asynchronous data transfers without
involving the host CPU. Currently, this framework can be
used to offload memory copies in the network stack and
RAID operations in the [31mCONFIG_MD[0m driver. This menu only presents
DMA Device drivers supported by the configured arch, it may
be empty in some cases.
config [31mCONFIG_DMADEVICES_DEBUG[0m
bool "DMA Engine debugging"
depends on [31mCONFIG_DMADEVICES[0m != n
help
This is an option for use by developers; most people should
say N here. This enables DMA engine core and driver debugging.
config [31mCONFIG_DMADEVICES_VDEBUG[0m
bool "DMA Engine verbose debugging"
depends on [31mCONFIG_DMADEVICES_DEBUG[0m != n
help
This is an option for use by developers; most people should
say N here. This enables deeper (more verbose) debugging of
the DMA engine core and drivers.
if [31mCONFIG_DMADEVICES[0m
comment "DMA Devices"
#core
config [31mCONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH[0m
bool
config [31mCONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL[0m
bool
config [31mCONFIG_DMA_ENGINE[0m
bool
config [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
tristate
config [31mCONFIG_DMA_ACPI[0m
def_bool y
depends on [31mCONFIG_ACPI[0m
config [31mCONFIG_DMA_OF[0m
def_bool y
depends on [31mCONFIG_OF[0m
select [31mCONFIG_DMA_ENGINE[0m
#devices
config [31mCONFIG_ALTERA_MSGDMA[0m
tristate "Altera / Intel mSGDMA Engine"
select [31mCONFIG_DMA_ENGINE[0m
help
Enable support for Altera / Intel mSGDMA controller.
config [31mCONFIG_AMBA_PL08X[0m
bool "ARM PrimeCell PL080 or PL081 support"
depends on [31mCONFIG_ARM_AMBA[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Say yes if your platform has a PL08x DMAC device which can
provide DMA engine support. This includes the original [31mCONFIG_ARM[0m
PL080 and PL081, Samsungs PL080 derivative and Faraday
Technology's FTDMAC020 PL080 derivative.
config [31mCONFIG_AMCC_PPC440SPE_ADMA[0m
tristate "AMCC PPC440SPe ADMA support"
depends on [31mCONFIG_440SPe[0m || [31mCONFIG_440SP[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_ENGINE_RAID[0m
select [31mCONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL[0m
select [31mCONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH[0m
help
Enable support for the AMCC PPC440SPe RAID engines.
config [31mCONFIG_AT_HDMAC[0m
tristate "Atmel AHB DMA support"
depends on [31mCONFIG_ARCH_AT91[0m
select [31mCONFIG_DMA_ENGINE[0m
help
Support the Atmel AHB DMA controller.
config [31mCONFIG_AT_XDMAC[0m
tristate "Atmel XDMA support"
depends on [31mCONFIG_ARCH_AT91[0m
select [31mCONFIG_DMA_ENGINE[0m
help
Support the Atmel XDMA controller.
config [31mCONFIG_AXI_DMAC[0m
tristate "Analog Devices AXI-DMAC DMA support"
depends on [31mCONFIG_MICROBLAZE[0m || [31mCONFIG_NIOS2[0m || [31mCONFIG_ARCH_ZYNQ[0m || [31mCONFIG_ARCH_ZYNQMP[0m || [31mCONFIG_ARCH_SOCFPGA[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
select [31mCONFIG_REGMAP_MMIO[0m
help
Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
controller is often used in Analog Device's reference designs for [31mCONFIG_FPGA[0m
platforms.
config [31mCONFIG_BCM_SBA_RAID[0m
tristate "Broadcom SBA RAID engine support"
depends on [31mCONFIG_ARM64[0m || [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_MAILBOX[0m && [31mCONFIG_RAID6_PQ[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_ENGINE_RAID[0m
select [31mCONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA[0m
select [31mCONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA[0m
default m if [31mCONFIG_ARCH_BCM_IPROC[0m
help
Enable support for Broadcom SBA RAID Engine. The SBA RAID
engine is available on most of the Broadcom iProc SoCs. It
has the capability to offload memcpy, xor and pq computation
for raid5/6.
config [31mCONFIG_COH901318[0m
bool "ST-Ericsson COH901318 DMA support"
select [31mCONFIG_DMA_ENGINE[0m
depends on [31mCONFIG_ARCH_U300[0m || [31mCONFIG_COMPILE_TEST[0m
help
Enable support for ST-Ericsson COH 901 318 DMA.
config [31mCONFIG_DMA_BCM2835[0m
tristate "BCM2835 DMA engine support"
depends on [31mCONFIG_ARCH_BCM2835[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
config [31mCONFIG_DMA_JZ4780[0m
tristate "JZ4780 DMA support"
depends on [31mCONFIG_MIPS[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
This selects support for the DMA controller in Ingenic JZ4780 SoCs.
If you have a board based on such a SoC and wish to use DMA for
devices which can use the DMA controller, say Y or [31mCONFIG_M[0m here.
config [31mCONFIG_DMA_SA11X0[0m
tristate "SA-11x0 DMA support"
depends on [31mCONFIG_ARCH_SA1100[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Support the DMA engine found on Intel StrongARM SA-1100 and
SA-1110 SoCs. This DMA engine can only be used with on-chip
devices.
config [31mCONFIG_DMA_SUN4I[0m
tristate "Allwinner A10 DMA SoCs support"
depends on [31mCONFIG_MACH_SUN4I[0m || [31mCONFIG_MACH_SUN5I[0m || [31mCONFIG_MACH_SUN7I[0m
default ([31mCONFIG_MACH_SUN4I[0m || [31mCONFIG_MACH_SUN5I[0m || [31mCONFIG_MACH_SUN7I[0m)
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Enable support for the DMA controller present in the sun4i,
sun5i and sun7i Allwinner [31mCONFIG_ARM[0m SoCs.
config [31mCONFIG_DMA_SUN6I[0m
tristate "Allwinner A31 SoCs DMA support"
depends on [31mCONFIG_MACH_SUN6I[0m || [31mCONFIG_MACH_SUN8I[0m || ([31mCONFIG_ARM64[0m && [31mCONFIG_ARCH_SUNXI[0m) || [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_RESET_CONTROLLER[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Support for the DMA engine first found in Allwinner A31 SoCs.
config [31mCONFIG_DW_AXI_DMAC[0m
tristate "Synopsys DesignWare AXI DMA support"
depends on [31mCONFIG_OF[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Enable support for Synopsys DesignWare AXI DMA controller.
NOTE: This driver wasn't tested on 64 bit platform because
of lack 64 bit platform with Synopsys DW AXI DMAC.
config [31mCONFIG_EP93XX_DMA[0m
bool "Cirrus Logic EP93xx DMA support"
depends on [31mCONFIG_ARCH_EP93XX[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
help
Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
config [31mCONFIG_FSL_DMA[0m
tristate "Freescale Elo series DMA support"
depends on [31mCONFIG_FSL_SOC[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH[0m
---help---
Enable support for the Freescale Elo series DMA controllers.
The Elo is the DMA controller on some mpc82xx and mpc83xx parts, the
EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on
some Txxx and Bxxx parts.
config [31mCONFIG_FSL_EDMA[0m
tristate "Freescale eDMA engine support"
depends on [31mCONFIG_OF[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Support the Freescale eDMA engine with programmable channel
multiplexing capability for DMA request sources(slot).
This module can be found on Freescale Vybrid and LS-1 SoCs.
config [31mCONFIG_FSL_QDMA[0m
tristate "NXP Layerscape qDMA engine support"
depends on [31mCONFIG_ARM[0m || [31mCONFIG_ARM64[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
select [31mCONFIG_DMA_ENGINE_RAID[0m
select [31mCONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH[0m
help
Support the NXP Layerscape qDMA engine with command queue and legacy mode.
Channel virtualization is supported through enqueuing of DMA jobs to,
or dequeuing DMA jobs from, different work queues.
This module can be found on NXP Layerscape SoCs.
The qdma driver only work on SoCs with a DPAA hardware block.
config [31mCONFIG_FSL_RAID[0m
tristate "Freescale RAID engine Support"
depends on [31mCONFIG_FSL_SOC[0m && ![31mCONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_ENGINE_RAID[0m
---help---
Enable support for Freescale RAID Engine. RAID Engine is
available on some QorIQ SoCs (like P5020/P5040). It has
the capability to offload memcpy, xor and pq computation
for raid5/6.
config [31mCONFIG_IMG_MDC_DMA[0m
tristate "IMG MDC support"
depends on [31mCONFIG_MIPS[0m || [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_MFD_SYSCON[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Enable support for the IMG multi-threaded DMA controller (MDC).
config [31mCONFIG_IMX_DMA[0m
tristate "i.MX DMA support"
depends on [31mCONFIG_ARCH_MXC[0m
select [31mCONFIG_DMA_ENGINE[0m
help
Support the i.MX DMA engine. This engine is integrated into
Freescale i.MX1/21/27 chips.
config [31mCONFIG_IMX_SDMA[0m
tristate "i.MX SDMA support"
depends on [31mCONFIG_ARCH_MXC[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Support the i.MX SDMA engine. This engine is integrated into
Freescale i.MX25/31/35/51/53/6 chips.
config [31mCONFIG_INTEL_IDMA64[0m
tristate "Intel integrated DMA 64-bit support"
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Enable DMA support for Intel Low Power Subsystem such as found on
Intel Skylake PCH.
config [31mCONFIG_INTEL_IOATDMA[0m
tristate "Intel I/OAT DMA support"
depends on [31mCONFIG_PCI[0m && [31mCONFIG_X86_64[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_ENGINE_RAID[0m
select [31mCONFIG_DCA[0m
help
Enable support for the Intel(R) I/OAT DMA engine present
in recent Intel Xeon chipsets.
Say Y here if you have such a chipset.
If unsure, say N.
config [31mCONFIG_INTEL_IOP_ADMA[0m
tristate "Intel IOP32x ADMA support"
depends on [31mCONFIG_ARCH_IOP32X[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH[0m
help
Enable support for the Intel(R) IOP Series RAID engines.
config [31mCONFIG_INTEL_MIC_X100_DMA[0m
tristate "Intel MIC X100 DMA Driver"
depends on [31mCONFIG_64BIT[0m && [31mCONFIG_X86[0m && [31mCONFIG_INTEL_MIC_BUS[0m
select [31mCONFIG_DMA_ENGINE[0m
help
This enables DMA support for the Intel Many Integrated Core
(MIC) family of PCIe form factor coprocessor X100 devices that
run a 64 bit Linux OS. This driver will be used by both MIC
host and card drivers.
If you are building host kernel with a MIC device or a card
kernel for a MIC device, then say [31mCONFIG_M[0m (recommended) or Y, else
say N. If unsure say N.
More information about the Intel MIC family as well as the Linux
OS and tools for MIC to use with this driver are available from
<http://software.intel.com/en-us/mic-developer>.
config [31mCONFIG_K3_DMA[0m
tristate "Hisilicon K3 DMA support"
depends on [31mCONFIG_ARCH_HI3xxx[0m || [31mCONFIG_ARCH_HISI[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Support the DMA engine for Hisilicon K3 platform
devices.
config [31mCONFIG_LPC18XX_DMAMUX[0m
bool "NXP LPC18xx/43xx DMA MUX for PL080"
depends on [31mCONFIG_ARCH_LPC18XX[0m || [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_OF[0m && [31mCONFIG_AMBA_PL08X[0m
select [31mCONFIG_MFD_SYSCON[0m
help
Enable support for DMA on NXP LPC18xx/43xx platforms
with PL080 and multiplexed DMA request lines.
config [31mCONFIG_MCF_EDMA[0m
tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"
depends on [31mCONFIG_M5441x[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Support the Freescale ColdFire eDMA engine, 64-channel
implementation that performs complex data transfers with
minimal intervention from a host processor.
This module can be found on Freescale ColdFire mcf5441x SoCs.
config [31mCONFIG_MMP_PDMA[0m
bool "MMP PDMA support"
depends on [31mCONFIG_ARCH_MMP[0m || [31mCONFIG_ARCH_PXA[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
help
Support the MMP PDMA engine for PXA and MMP platform.
config [31mCONFIG_MMP_TDMA[0m
bool "MMP Two-Channel DMA support"
depends on [31mCONFIG_ARCH_MMP[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_MMP_SRAM[0m if [31mCONFIG_ARCH_MMP[0m
select [31mCONFIG_GENERIC_ALLOCATOR[0m
help
Support the MMP Two-Channel DMA engine.
This engine used for MMP Audio DMA and pxa910 SQU.
It needs sram driver under mach-mmp.
config [31mCONFIG_MOXART_DMA[0m
tristate "MOXART DMA support"
depends on [31mCONFIG_ARCH_MOXART[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Enable support for the MOXA ART SoC DMA controller.
Say Y here if you enabled MMP ADMA, otherwise say N.
config [31mCONFIG_MPC512X_DMA[0m
tristate "Freescale MPC512x built-in DMA engine support"
depends on [31mCONFIG_PPC_MPC512x[0m || [31mCONFIG_PPC_MPC831x[0m
select [31mCONFIG_DMA_ENGINE[0m
---help---
Enable support for the Freescale MPC512x built-in DMA engine.
config [31mCONFIG_MV_XOR[0m
bool "Marvell XOR engine support"
depends on [31mCONFIG_PLAT_ORION[0m || [31mCONFIG_ARCH_MVEBU[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_ENGINE_RAID[0m
select [31mCONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH[0m
---help---
Enable support for the Marvell XOR engine.
config [31mCONFIG_MV_XOR_V2[0m
bool "Marvell XOR engine version 2 support "
depends on [31mCONFIG_ARM64[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_ENGINE_RAID[0m
select [31mCONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH[0m
select [31mCONFIG_GENERIC_MSI_IRQ_DOMAIN[0m
---help---
Enable support for the Marvell version 2 XOR engine.
This engine provides acceleration for copy, XOR and RAID6
operations, and is available on Marvell Armada 7K and 8K
platforms.
config [31mCONFIG_MXS_DMA[0m
bool "MXS DMA support"
depends on [31mCONFIG_ARCH_MXS[0m || [31mCONFIG_ARCH_MXC[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_STMP_DEVICE[0m
select [31mCONFIG_DMA_ENGINE[0m
help
Support the MXS DMA engine. This engine including APBH-DMA
and APBX-DMA is integrated into some Freescale chips.
config [31mCONFIG_MX3_IPU[0m
bool "MX3x Image Processing Unit support"
depends on [31mCONFIG_ARCH_MXC[0m
select [31mCONFIG_DMA_ENGINE[0m
default y
help
If you plan to use the Image Processing unit in the i.MX3x, say
Y here. If unsure, select Y.
config [31mCONFIG_MX3_IPU_IRQS[0m
int "Number of dynamically mapped interrupts for IPU"
depends on [31mCONFIG_MX3_IPU[0m
range 2 137
default 4
help
Out of 137 interrupt sources on i.MX31 IPU only very few are used.
To avoid bloating the irq_desc[] array we allocate a sufficient
number of IRQ slots and map them dynamically to specific sources.
config [31mCONFIG_NBPFAXI_DMA[0m
tristate "Renesas Type-AXI NBPF DMA support"
select [31mCONFIG_DMA_ENGINE[0m
depends on [31mCONFIG_ARM[0m || [31mCONFIG_COMPILE_TEST[0m
help
Support for "Type-AXI" NBPF DMA IPs from Renesas
config [31mCONFIG_OWL_DMA[0m
tristate "Actions Semi Owl SoCs DMA support"
depends on [31mCONFIG_ARCH_ACTIONS[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Enable support for the Actions Semi Owl SoCs DMA controller.
config [31mCONFIG_PCH_DMA[0m
tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
depends on [31mCONFIG_PCI[0m && ([31mCONFIG_X86_32[0m || [31mCONFIG_COMPILE_TEST[0m)
select [31mCONFIG_DMA_ENGINE[0m
help
Enable support for Intel EG20T PCH DMA engine.
This driver also can be used for LAPIS Semiconductor IOH(Input/
Output Hub), ML7213, ML7223 and ML7831.
ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
for MP(Media Phone) use and ML7831 IOH is for general purpose use.
ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
config [31mCONFIG_PL330_DMA[0m
tristate "DMA API Driver for PL330"
select [31mCONFIG_DMA_ENGINE[0m
depends on [31mCONFIG_ARM_AMBA[0m
help
Select if your platform has one or more PL330 DMACs.
You need to provide platform specific settings via
platform_data for a dma-pl330 device.
config [31mCONFIG_PXA_DMA[0m
bool "PXA DMA support"
depends on ([31mCONFIG_ARCH_MMP[0m || [31mCONFIG_ARCH_PXA[0m)
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Support the DMA engine for PXA. It is also compatible with MMP PDMA
platform. The internal DMA IP of all PXA variants is supported, with
16 to 32 channels for peripheral to memory or memory to memory
transfers.
config [31mCONFIG_SIRF_DMA[0m
tristate "CSR SiRFprimaII/SiRFmarco DMA support"
depends on [31mCONFIG_ARCH_SIRF[0m
select [31mCONFIG_DMA_ENGINE[0m
help
Enable support for the CSR SiRFprimaII DMA engine.
config [31mCONFIG_STE_DMA40[0m
bool "ST-Ericsson DMA40 support"
depends on [31mCONFIG_ARCH_U8500[0m
select [31mCONFIG_DMA_ENGINE[0m
help
Support for ST-Ericsson DMA40 controller
config [31mCONFIG_ST_FDMA[0m
tristate "ST FDMA dmaengine support"
depends on [31mCONFIG_ARCH_STI[0m
depends on [31mCONFIG_REMOTEPROC[0m
select [31mCONFIG_ST_SLIM_REMOTEPROC[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Enable support for ST FDMA controller.
It supports 16 independent DMA channels, accepts up to 32 DMA requests
Say Y here if you have such a chipset.
If unsure, say N.
config [31mCONFIG_STM32_DMA[0m
bool "STMicroelectronics STM32 DMA support"
depends on [31mCONFIG_ARCH_STM32[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Enable support for the on-chip DMA controller on STMicroelectronics
STM32 MCUs.
If you have a board based on such a MCU and wish to use DMA say Y
here.
config [31mCONFIG_STM32_DMAMUX[0m
bool "STMicroelectronics STM32 dma multiplexer support"
depends on [31mCONFIG_STM32_DMA[0m || [31mCONFIG_COMPILE_TEST[0m
help
Enable support for the on-chip DMA multiplexer on STMicroelectronics
STM32 MCUs.
If you have a board based on such a MCU and wish to use DMAMUX say Y
here.
config [31mCONFIG_STM32_MDMA[0m
bool "STMicroelectronics STM32 master dma support"
depends on [31mCONFIG_ARCH_STM32[0m || [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_OF[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Enable support for the on-chip MDMA controller on STMicroelectronics
STM32 platforms.
If you have a board based on STM32 SoC and wish to use the master DMA
say Y here.
config [31mCONFIG_SPRD_DMA[0m
tristate "Spreadtrum DMA support"
depends on [31mCONFIG_ARCH_SPRD[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Enable support for the on-chip DMA controller on Spreadtrum platform.
config [31mCONFIG_S3C24XX_DMAC[0m
bool "Samsung S3C24XX DMA support"
depends on [31mCONFIG_ARCH_S3C24XX[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Support for the Samsung S3C24XX DMA controller driver. The
DMA controller is having multiple DMA channels which can be
configured for different peripherals like audio, UART, [31mCONFIG_SPI[0m.
The DMA controller can transfer data from memory to peripheral,
periphal to memory, periphal to periphal and memory to memory.
config [31mCONFIG_TXX9_DMAC[0m
tristate "Toshiba TXx9 SoC DMA support"
depends on [31mCONFIG_MACH_TX49XX[0m || [31mCONFIG_MACH_TX39XX[0m
select [31mCONFIG_DMA_ENGINE[0m
help
Support the TXx9 SoC internal DMA controller. This can be
integrated in chips such as the Toshiba TX4927/38/39.
config [31mCONFIG_TEGRA20_APB_DMA[0m
bool "NVIDIA Tegra20 APB DMA support"
depends on [31mCONFIG_ARCH_TEGRA[0m
select [31mCONFIG_DMA_ENGINE[0m
help
Support for the NVIDIA Tegra20 APB DMA controller driver. The
DMA controller is having multiple DMA channel which can be
configured for different peripherals like audio, UART, [31mCONFIG_SPI[0m,
[31mCONFIG_I2C[0m etc which is in APB bus.
This DMA controller transfers data from memory to peripheral fifo
or vice versa. It does not support memory to memory data transfer.
config [31mCONFIG_TEGRA210_ADMA[0m
tristate "NVIDIA Tegra210 ADMA support"
depends on ([31mCONFIG_ARCH_TEGRA_210_SOC[0m || [31mCONFIG_COMPILE_TEST[0m)
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Support for the NVIDIA Tegra210 ADMA controller driver. The
DMA controller has multiple DMA channels and is used to service
various audio clients in the Tegra210 audio processing engine
(APE). This DMA controller transfers data from memory to
peripheral and vice versa. It does not support memory to
memory data transfer.
config [31mCONFIG_TIMB_DMA[0m
tristate "Timberdale FPGA DMA support"
depends on [31mCONFIG_MFD_TIMBERDALE[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
help
Enable support for the Timberdale [31mCONFIG_FPGA[0m DMA engine.
config [31mCONFIG_UNIPHIER_MDMAC[0m
tristate "UniPhier MIO DMAC"
depends on [31mCONFIG_ARCH_UNIPHIER[0m || [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_OF[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Enable support for the MIO DMAC (Media I/O DMA controller) on the
UniPhier platform. This DMA controller is used as the external
DMA engine of the SD/eMMC controllers of the LD4, Pro4, sLD8 SoCs.
config [31mCONFIG_XGENE_DMA[0m
tristate "APM X-Gene DMA support"
depends on [31mCONFIG_ARCH_XGENE[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_ENGINE_RAID[0m
select [31mCONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH[0m
help
Enable support for the [31mCONFIG_APM[0m X-Gene SoC DMA engine.
config [31mCONFIG_XILINX_DMA[0m
tristate "Xilinx AXI DMAS Engine"
depends on ([31mCONFIG_ARCH_ZYNQ[0m || [31mCONFIG_MICROBLAZE[0m || [31mCONFIG_ARM64[0m)
select [31mCONFIG_DMA_ENGINE[0m
help
Enable support for Xilinx AXI VDMA Soft IP.
AXI VDMA engine provides high-bandwidth direct memory access
between memory and AXI4-Stream video type target
peripherals including peripherals which support AXI4-
Stream Video Protocol. It has two stream interfaces/
channels, Memory Mapped to Stream (MM2S) and Stream to
Memory Mapped (S2MM) for the data transfers.
AXI CDMA engine provides high-bandwidth direct memory access
between a memory-mapped source address and a memory-mapped
destination address.
AXI DMA engine provides high-bandwidth one dimensional direct
memory access between memory and AXI4-Stream target peripherals.
config [31mCONFIG_XILINX_ZYNQMP_DMA[0m
tristate "Xilinx ZynqMP DMA Engine"
depends on ([31mCONFIG_ARCH_ZYNQ[0m || [31mCONFIG_MICROBLAZE[0m || [31mCONFIG_ARM64[0m)
select [31mCONFIG_DMA_ENGINE[0m
help
Enable support for Xilinx ZynqMP DMA controller.
config [31mCONFIG_ZX_DMA[0m
tristate "ZTE ZX DMA support"
depends on [31mCONFIG_ARCH_ZX[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_VIRTUAL_CHANNELS[0m
help
Support the DMA engine for ZTE ZX family platform devices.
# driver files
source "drivers/dma/bestcomm/Kconfig"
source "drivers/dma/mediatek/Kconfig"
source "drivers/dma/qcom/Kconfig"
source "drivers/dma/dw/Kconfig"
source "drivers/dma/dw-edma/Kconfig"
source "drivers/dma/hsu/Kconfig"
source "drivers/dma/sh/Kconfig"
source "drivers/dma/ti/Kconfig"
# clients
comment "DMA Clients"
depends on [31mCONFIG_DMA_ENGINE[0m
config [31mCONFIG_ASYNC_TX_DMA[0m
bool "Async_tx: Offload support for the async_tx api"
depends on [31mCONFIG_DMA_ENGINE[0m
help
This allows the async_tx api to take advantage of offload engines for
memcpy, memset, xor, and raid6 p+q operations. If your platform has
a dma engine that can perform raid operations and you have enabled
[31mCONFIG_MD_RAID456[0m say Y.
If unsure, say N.
config [31mCONFIG_DMATEST[0m
tristate "DMA Test client"
depends on [31mCONFIG_DMA_ENGINE[0m
select [31mCONFIG_DMA_ENGINE_RAID[0m
help
Simple DMA test client. Say N unless you're debugging a
DMA Device driver.
config [31mCONFIG_DMA_ENGINE_RAID[0m
bool
endif