# SPDX-License-Identifier: GPL-2.0-only
comment "Processor Features"
config [31mCONFIG_CPU_BIG_ENDIAN[0m
def_bool ![31mCONFIG_CPU_LITTLE_ENDIAN[0m
config [31mCONFIG_CPU_LITTLE_ENDIAN[0m
bool "Little endian"
default y
config [31mCONFIG_FPU[0m
bool "FPU support"
default n
help
If [31mCONFIG_FPU[0m [31mCONFIG_ISA[0m is used in user space, this configuration shall be Y to
enable required support in kerenl such as fpu context switch and
fpu exception handler.
If no [31mCONFIG_FPU[0m [31mCONFIG_ISA[0m is used in user space, say N.
config [31mCONFIG_LAZY_FPU[0m
bool "lazy FPU support"
depends on [31mCONFIG_FPU[0m
default y
help
Say Y here to enable the lazy [31mCONFIG_FPU[0m scheme. The lazy [31mCONFIG_FPU[0m scheme can
enhance system performance by reducing the context switch
frequency of the [31mCONFIG_FPU[0m register.
For nomal case, say Y.
config [31mCONFIG_SUPPORT_DENORMAL_ARITHMETIC[0m
bool "Denormal arithmetic support"
depends on [31mCONFIG_FPU[0m
default n
help
Say Y here to enable arithmetic of denormalized number. Enabling
this feature can enhance the precision for tininess number.
However, performance loss in float pointe calculations is
possibly significant due to additional [31mCONFIG_FPU[0m exception.
If the calculated tolerance for tininess number is not critical,
say N to prevent performance loss.
config [31mCONFIG_HWZOL[0m
bool "hardware zero overhead loop support"
depends on [31mCONFIG_CPU_D10[0m || [31mCONFIG_CPU_D15[0m
default n
help
[31mCONFIG_A[0m set of Zero-Overhead Loop mechanism is provided to reduce the
instruction fetch and execution overhead of loop-control instructions.
It will save 3 registers($LB, $LC, $LE) for context saving if say Y.
You don't need to save these registers if you can make sure your user
program doesn't use these registers.
If unsure, say N.
config [31mCONFIG_CPU_CACHE_ALIASING[0m
bool "Aliasing cache"
depends on [31mCONFIG_CPU_N10[0m || [31mCONFIG_CPU_D10[0m || [31mCONFIG_CPU_N13[0m || [31mCONFIG_CPU_V3[0m
default y
help
If this CPU is using VIPT data cache and its cache way size is larger
than page size, say Y. If it is using PIPT data cache, say N.
If unsure, say Y.
choice
prompt "minimum CPU type"
default [31mCONFIG_CPU_V3[0m
help
The data cache of N15/D15 is implemented as PIPT and it will not cause
the cache aliasing issue. The rest cpus(N13, N10 and D10) are
implemented as VIPT data cache. It may cause the cache aliasing issue
if its cache way size is larger than page size. You can specify the
CPU type direcly or choose [31mCONFIG_CPU_V3[0m if unsure.
[31mCONFIG_A[0m kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
[31mCONFIG_A[0m kernel built for N15 is able to run on N15 or D15.
[31mCONFIG_A[0m kernel built for D10 is able to run on D10 or D15.
[31mCONFIG_A[0m kernel built for D15 is able to run on D15.
[31mCONFIG_A[0m kernel built for N13 is able to run on N15, N13 or D15.
config [31mCONFIG_CPU_N15[0m
bool "AndesCore N15"
config [31mCONFIG_CPU_N13[0m
bool "AndesCore N13"
select [31mCONFIG_CPU_CACHE_ALIASING[0m if [31mCONFIG_ANDES_PAGE_SIZE_4KB[0m
config [31mCONFIG_CPU_N10[0m
bool "AndesCore N10"
select [31mCONFIG_CPU_CACHE_ALIASING[0m
config [31mCONFIG_CPU_D15[0m
bool "AndesCore D15"
config [31mCONFIG_CPU_D10[0m
bool "AndesCore D10"
select [31mCONFIG_CPU_CACHE_ALIASING[0m
config [31mCONFIG_CPU_V3[0m
bool "AndesCore v3 compatible"
select [31mCONFIG_CPU_CACHE_ALIASING[0m
endchoice
choice
prompt "Paging -- page size "
default [31mCONFIG_ANDES_PAGE_SIZE_4KB[0m
config [31mCONFIG_ANDES_PAGE_SIZE_4KB[0m
bool "use 4KB page size"
config [31mCONFIG_ANDES_PAGE_SIZE_8KB[0m
bool "use 8KB page size"
endchoice
config [31mCONFIG_CPU_ICACHE_DISABLE[0m
bool "Disable I-Cache"
help
Say Y here to disable the processor instruction cache. Unless
you have a reason not to or are unsure, say N.
config [31mCONFIG_CPU_DCACHE_DISABLE[0m
bool "Disable D-Cache"
help
Say Y here to disable the processor data cache. Unless
you have a reason not to or are unsure, say N.
config [31mCONFIG_CPU_DCACHE_WRITETHROUGH[0m
bool "Force write through D-cache"
depends on ![31mCONFIG_CPU_DCACHE_DISABLE[0m
help
Say Y here to use the data cache in writethrough mode. Unless you
specifically require this or are unsure, say N.
config [31mCONFIG_WBNA[0m
bool "WBNA"
default n
help
Say Y here to enable write-back memory with no-write-allocation policy.
config [31mCONFIG_ALIGNMENT_TRAP[0m
bool "Kernel support unaligned access handling by sw"
depends on [31mCONFIG_PROC_FS[0m
default n
help
Andes processors cannot load/store information which is not
naturally aligned on the bus, i.e., a 4 byte load must start at an
address divisible by 4. On 32-bit Andes processors, these non-aligned
load/store instructions will be emulated in software if you say Y
here, which has a severe performance impact. With an IP-only
configuration it is safe to say N, otherwise say Y.
config [31mCONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS[0m
bool "Kernel support unaligned access handling by hw"
depends on ![31mCONFIG_ALIGNMENT_TRAP[0m
default n
help
Andes processors load/store world/half-word instructions can access
unaligned memory locations without generating the Data Alignment
Check exceptions. With an IP-only configuration it is safe to say N,
otherwise say Y.
config [31mCONFIG_HIGHMEM[0m
bool "High Memory Support"
depends on [31mCONFIG_MMU[0m && ![31mCONFIG_CPU_CACHE_ALIASING[0m
help
The address space of Andes processors is only 4 Gigabytes large
and it has to accommodate user address space, kernel address
space as well as some memory mapped IO. That means that, if you
have a large amount of physical memory and/or IO, not all of the
memory can be "permanently mapped" by the kernel. The physical
memory that is not permanently mapped is called "high memory".
Depending on the selected kernel/user memory split, minimum
vmalloc space and actual amount of RAM, you may not need this
option which should result in a slightly faster kernel.
If unsure, say N.
config [31mCONFIG_CACHE_L2[0m
bool "Support L2 cache"
default y
help
Say Y here to enable L2 cache if your SoC are integrated with L2CC.
If unsure, say N.
config [31mCONFIG_HW_PRE[0m
bool "Enable hardware prefetcher"
default y
help
Say Y here to enable hardware prefetcher feature.
Only when CPU_VER.REV >= 0x09 can support.
menu "Memory configuration"
choice
prompt "Memory split"
depends on [31mCONFIG_MMU[0m
default [31mCONFIG_VMSPLIT_3G_OPT[0m
help
Select the desired split between kernel and user memory.
If you are not absolutely sure what you are doing, leave this
option alone!
config [31mCONFIG_VMSPLIT_3G[0m
bool "3G/1G user/kernel split"
config [31mCONFIG_VMSPLIT_3G_OPT[0m
bool "3G/1G user/kernel split (for full 1G low memory)"
config [31mCONFIG_VMSPLIT_2G[0m
bool "2G/2G user/kernel split"
config [31mCONFIG_VMSPLIT_1G[0m
bool "1G/3G user/kernel split"
endchoice
config [31mCONFIG_PAGE_OFFSET[0m
hex
default 0x40000000 if [31mCONFIG_VMSPLIT_1G[0m
default 0x80000000 if [31mCONFIG_VMSPLIT_2G[0m
default 0xB0000000 if [31mCONFIG_VMSPLIT_3G_OPT[0m
default 0xC0000000
endmenu