# SPDX-License-Identifier: GPL-2.0-only
menu "Clock Source drivers"
depends on [31mCONFIG_GENERIC_CLOCKEVENTS[0m
config [31mCONFIG_TIMER_OF[0m
bool
select [31mCONFIG_TIMER_PROBE[0m
config [31mCONFIG_TIMER_ACPI[0m
bool
select [31mCONFIG_TIMER_PROBE[0m
config [31mCONFIG_TIMER_PROBE[0m
bool
config [31mCONFIG_CLKSRC_I8253[0m
bool
config [31mCONFIG_CLKEVT_I8253[0m
bool
config [31mCONFIG_I8253_LOCK[0m
bool
config [31mCONFIG_OMAP_DM_TIMER[0m
bool
config [31mCONFIG_CLKBLD_I8253[0m
def_bool y if [31mCONFIG_CLKSRC_I8253[0m || [31mCONFIG_CLKEVT_I8253[0m || [31mCONFIG_I8253_LOCK[0m
config [31mCONFIG_CLKSRC_MMIO[0m
bool
config [31mCONFIG_BCM2835_TIMER[0m
bool "BCM2835 timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables the support for the BCM2835 timer driver.
config [31mCONFIG_BCM_KONA_TIMER[0m
bool "BCM mobile timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables the support for the BCM Kona mobile timer driver.
config [31mCONFIG_DAVINCI_TIMER[0m
bool "Texas Instruments DaVinci timer driver" if [31mCONFIG_COMPILE_TEST[0m
help
Enables the support for the TI DaVinci timer driver.
config [31mCONFIG_DIGICOLOR_TIMER[0m
bool "Digicolor timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
depends on [31mCONFIG_HAS_IOMEM[0m
help
Enables the support for the digicolor timer driver.
config [31mCONFIG_DW_APB_TIMER[0m
bool "DW APB timer driver" if [31mCONFIG_COMPILE_TEST[0m
help
Enables the support for the dw_apb timer.
config [31mCONFIG_DW_APB_TIMER_OF[0m
bool
select [31mCONFIG_DW_APB_TIMER[0m
select [31mCONFIG_TIMER_OF[0m
config [31mCONFIG_FTTMR010_TIMER[0m
bool "Faraday Technology timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_TIMER_OF[0m
select [31mCONFIG_MFD_SYSCON[0m
help
Enables support for the Faraday Technology timer block
FTTMR010.
config [31mCONFIG_IXP4XX_TIMER[0m
bool "Intel XScale IXP4xx timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables support for the Intel XScale IXP4xx SoC timer.
config [31mCONFIG_ROCKCHIP_TIMER[0m
bool "Rockchip timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_ARM[0m || [31mCONFIG_ARM64[0m
select [31mCONFIG_TIMER_OF[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables the support for the rockchip timer driver.
config [31mCONFIG_ARMADA_370_XP_TIMER[0m
bool "Armada 370 and XP timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_ARM[0m
select [31mCONFIG_TIMER_OF[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables the support for the Armada 370 and XP timer driver.
config [31mCONFIG_MESON6_TIMER[0m
bool "Meson6 timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables the support for the Meson6 timer driver.
config [31mCONFIG_ORION_TIMER[0m
bool "Orion timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_ARM[0m
select [31mCONFIG_TIMER_OF[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables the support for the Orion timer driver
config [31mCONFIG_OWL_TIMER[0m
bool "Owl timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables the support for the Actions Semi Owl timer driver.
config [31mCONFIG_RDA_TIMER[0m
bool "RDA timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_TIMER_OF[0m
help
Enables the support for the RDA Micro timer driver.
config [31mCONFIG_SUN4I_TIMER[0m
bool "Sun4i timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_TIMER_OF[0m
help
Enables support for the Sun4i timer.
config [31mCONFIG_SUN5I_HSTIMER[0m
bool "Sun5i timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
depends on [31mCONFIG_COMMON_CLK[0m
help
Enables support the Sun5i timer.
config [31mCONFIG_TEGRA_TIMER[0m
bool "Tegra timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_TIMER_OF[0m
depends on [31mCONFIG_ARCH_TEGRA[0m || [31mCONFIG_COMPILE_TEST[0m
help
Enables support for the Tegra driver.
config [31mCONFIG_VT8500_TIMER[0m
bool "VT8500 timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
help
Enables support for the VT8500 driver.
config [31mCONFIG_NPCM7XX_TIMER[0m
bool "NPCM7xx timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_TIMER_OF[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enable 24-bit [31mCONFIG_TIMER0[0m and [31mCONFIG_TIMER1[0m counters in the NPCM7xx architecture,
While [31mCONFIG_TIMER0[0m serves as clockevent and [31mCONFIG_TIMER1[0m serves as clocksource.
config [31mCONFIG_CADENCE_TTC_TIMER[0m
bool "Cadence TTC timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_COMMON_CLK[0m
help
Enables support for the cadence ttc driver.
config [31mCONFIG_ASM9260_TIMER[0m
bool "ASM9260 timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_TIMER_OF[0m
help
Enables support for the ASM9260 timer.
config [31mCONFIG_CLKSRC_NOMADIK_MTU[0m
bool "Nomakdik clocksource driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_ARM[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Support for Multi Timer Unit. MTU provides access
to multiple interrupt generating programmable
32-bit free running decrementing counters.
config [31mCONFIG_CLKSRC_DBX500_PRCMU[0m
bool "Clocksource PRCMU Timer" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
help
Use the always on PRCMU Timer as clocksource
config [31mCONFIG_CLPS711X_TIMER[0m
bool "Cirrus logic timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables support for the Cirrus Logic PS711 timer.
config [31mCONFIG_ATLAS7_TIMER[0m
bool "Atlas7 timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables support for the Atlas7 timer.
config [31mCONFIG_MXS_TIMER[0m
bool "Mxs timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_STMP_DEVICE[0m
help
Enables support for the Mxs timer.
config [31mCONFIG_PRIMA2_TIMER[0m
bool "Prima2 timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables support for the Prima2 timer.
config [31mCONFIG_U300_TIMER[0m
bool "U300 timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_ARM[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables support for the U300 timer.
config [31mCONFIG_NSPIRE_TIMER[0m
bool "NSpire timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables support for the Nspire timer.
config [31mCONFIG_KEYSTONE_TIMER[0m
bool "Keystone timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_ARM[0m || [31mCONFIG_ARM64[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables support for the Keystone timer.
config [31mCONFIG_INTEGRATOR_AP_TIMER[0m
bool "Integrator-ap timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables support for the Integrator-ap timer.
config [31mCONFIG_CLKSRC_EFM32[0m
bool "Clocksource for Energy Micro's EFM32 SoCs" if ![31mCONFIG_ARCH_EFM32[0m
depends on [31mCONFIG_OF[0m && [31mCONFIG_ARM[0m && ([31mCONFIG_ARCH_EFM32[0m || [31mCONFIG_COMPILE_TEST[0m)
select [31mCONFIG_CLKSRC_MMIO[0m
default [31mCONFIG_ARCH_EFM32[0m
help
Support to use the timers of EFM32 SoCs as clock source and clock
event device.
config [31mCONFIG_CLKSRC_LPC32XX[0m
bool "Clocksource for LPC32XX" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
depends on [31mCONFIG_ARM[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_TIMER_OF[0m
help
Support for the LPC32XX clocksource.
config [31mCONFIG_CLKSRC_PISTACHIO[0m
bool "Clocksource for Pistachio SoC" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_TIMER_OF[0m
help
Enables the clocksource for the Pistachio SoC.
config [31mCONFIG_CLKSRC_TI_32K[0m
bool "Texas Instruments 32.768 Hz Clocksource" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_GENERIC_SCHED_CLOCK[0m
select [31mCONFIG_TIMER_OF[0m if [31mCONFIG_OF[0m
help
This option enables support for Texas Instruments 32.768 Hz clocksource
available on many OMAP-like platforms.
config [31mCONFIG_CLKSRC_NPS[0m
bool "NPS400 clocksource driver" if [31mCONFIG_COMPILE_TEST[0m
depends on ![31mCONFIG_PHYS_ADDR_T_64BIT[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_TIMER_OF[0m if [31mCONFIG_OF[0m
help
NPS400 clocksource support.
Got 64 bit counter with update rate up to 1000MHz.
This counter is accessed via couple of 32 bit memory mapped registers.
config [31mCONFIG_CLKSRC_STM32[0m
bool "Clocksource for STM32 SoCs" if ![31mCONFIG_ARCH_STM32[0m
depends on [31mCONFIG_OF[0m && [31mCONFIG_ARM[0m && ([31mCONFIG_ARCH_STM32[0m || [31mCONFIG_COMPILE_TEST[0m)
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_TIMER_OF[0m
config [31mCONFIG_CLKSRC_MPS2[0m
bool "Clocksource for MPS2 SoCs" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_GENERIC_SCHED_CLOCK[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_TIMER_OF[0m
config [31mCONFIG_ARC_TIMERS[0m
bool "Support for 32-bit TIMERn counters in ARC Cores" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_GENERIC_SCHED_CLOCK[0m
select [31mCONFIG_TIMER_OF[0m
help
These are legacy 32-bit [31mCONFIG_TIMER0[0m and [31mCONFIG_TIMER1[0m counters found on all [31mCONFIG_ARC[0m cores
(ARC700 as well as [31mCONFIG_ARC[0m HS38).
[31mCONFIG_TIMER0[0m serves as clockevent while [31mCONFIG_TIMER1[0m provides clocksource
config [31mCONFIG_ARC_TIMERS_64BIT[0m
bool "Support for 64-bit counters in ARC HS38 cores" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_ARC_TIMERS[0m
select [31mCONFIG_TIMER_OF[0m
help
This enables 2 different 64-bit timers: [31mCONFIG_RTC[0m (for UP) and GFRC (for [31mCONFIG_SMP[0m)
[31mCONFIG_RTC[0m is implemented inside the core, while GFRC sits outside the core in
ARConnect IP block. Driver automatically picks one of them for clocksource
as appropriate.
config [31mCONFIG_ARM_ARCH_TIMER[0m
bool
select [31mCONFIG_TIMER_OF[0m if [31mCONFIG_OF[0m
select [31mCONFIG_TIMER_ACPI[0m if [31mCONFIG_ACPI[0m
config [31mCONFIG_ARM_ARCH_TIMER_EVTSTREAM[0m
bool "Enable ARM architected timer event stream generation by default"
default y if [31mCONFIG_ARM_ARCH_TIMER[0m
depends on [31mCONFIG_ARM_ARCH_TIMER[0m
help
This option enables support by default for event stream generation
based on the [31mCONFIG_ARM[0m architected timer. It is used for waking up CPUs
executing the wfe instruction at a frequency represented as a
power-of-2 divisor of the clock rate. The behaviour can also be
overridden on the command line using the
clocksource.arm_arch_timer.evtstream parameter.
The main use of the event stream is wfe-based timeouts of userspace
locking implementations. It might also be useful for imposing timeout
on wfe to safeguard against any programming errors in case an expected
event is not generated.
This must be disabled for hardware validation purposes to detect any
hardware anomalies of missing events.
config [31mCONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND[0m
bool
config [31mCONFIG_FSL_ERRATUM_A008585[0m
bool "Workaround for Freescale/NXP Erratum A-008585"
default y
depends on [31mCONFIG_ARM_ARCH_TIMER[0m && [31mCONFIG_ARM64[0m
select [31mCONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND[0m
help
This option enables a workaround for Freescale/NXP Erratum
[31mCONFIG_A[0m-008585 ("ARM generic timer may contain an erroneous
value"). The workaround will only be active if the
fsl,erratum-a008585 property is found in the timer node.
config [31mCONFIG_HISILICON_ERRATUM_161010101[0m
bool "Workaround for Hisilicon Erratum 161010101"
default y
select [31mCONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND[0m
depends on [31mCONFIG_ARM_ARCH_TIMER[0m && [31mCONFIG_ARM64[0m
help
This option enables a workaround for Hisilicon Erratum
161010101. The workaround will be active if the hisilicon,erratum-161010101
property is found in the timer node.
config [31mCONFIG_ARM64_ERRATUM_858921[0m
bool "Workaround for Cortex-A73 erratum 858921"
default y
select [31mCONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND[0m
depends on [31mCONFIG_ARM_ARCH_TIMER[0m && [31mCONFIG_ARM64[0m
help
This option enables a workaround applicable to Cortex-A73
(all versions), whose counter may return incorrect values.
The workaround will be dynamically enabled when an affected
core is detected.
config [31mCONFIG_SUN50I_ERRATUM_UNKNOWN1[0m
bool "Workaround for Allwinner A64 erratum UNKNOWN1"
default y
depends on [31mCONFIG_ARM_ARCH_TIMER[0m && [31mCONFIG_ARM64[0m && [31mCONFIG_ARCH_SUNXI[0m
select [31mCONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND[0m
help
This option enables a workaround for instability in the timer on
the Allwinner A64 SoC. The workaround will only be active if the
allwinner,erratum-unknown1 property is found in the timer node.
config [31mCONFIG_ARM_GLOBAL_TIMER[0m
bool "Support for the ARM global timer" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_TIMER_OF[0m if [31mCONFIG_OF[0m
depends on [31mCONFIG_ARM[0m
help
This options enables support for the [31mCONFIG_ARM[0m global timer unit
config [31mCONFIG_ARM_TIMER_SP804[0m
bool "Support for Dual Timer SP804 module" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_GENERIC_SCHED_CLOCK[0m && [31mCONFIG_CLKDEV_LOOKUP[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_TIMER_OF[0m if [31mCONFIG_OF[0m
config [31mCONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK[0m
bool
depends on [31mCONFIG_ARM_GLOBAL_TIMER[0m
default y
help
Use [31mCONFIG_ARM[0m global timer clock source as sched_clock
config [31mCONFIG_ARMV7M_SYSTICK[0m
bool "Support for the ARMv7M system time" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_TIMER_OF[0m if [31mCONFIG_OF[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
This options enables support for the ARMv7M system timer unit
config [31mCONFIG_ATMEL_PIT[0m
bool "Atmel PIT support" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_TIMER_OF[0m if [31mCONFIG_OF[0m
help
Support for the Periodic Interval Timer found on Atmel SoCs.
config [31mCONFIG_ATMEL_ST[0m
bool "Atmel ST timer support" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_TIMER_OF[0m
select [31mCONFIG_MFD_SYSCON[0m
help
Support for the Atmel ST timer.
config [31mCONFIG_ATMEL_TCB_CLKSRC[0m
bool "Atmel TC Block timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_ARM[0m && [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_TIMER_OF[0m if [31mCONFIG_OF[0m
help
Support for Timer Counter Blocks on Atmel SoCs.
config [31mCONFIG_CLKSRC_EXYNOS_MCT[0m
bool "Exynos multi core timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_ARM[0m || [31mCONFIG_ARM64[0m
help
Support for Multi Core Timer controller on Exynos SoCs.
config [31mCONFIG_CLKSRC_SAMSUNG_PWM[0m
bool "PWM timer driver for Samsung S3C, S5P" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
help
This is a new clocksource driver for the [31mCONFIG_PWM[0m timer found in
Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver
for all devicetree enabled platforms. This driver will be
needed only on systems that do not have the Exynos MCT available.
config [31mCONFIG_FSL_FTM_TIMER[0m
bool "Freescale FlexTimer Module driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Support for Freescale FlexTimer Module (FTM) timer.
config [31mCONFIG_VF_PIT_TIMER[0m
bool
select [31mCONFIG_CLKSRC_MMIO[0m
help
Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
config [31mCONFIG_OXNAS_RPS_TIMER[0m
bool "Oxford Semiconductor OXNAS RPS Timers driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_TIMER_OF[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
This enables support for the Oxford Semiconductor OXNAS [31mCONFIG_RPS[0m timers.
config [31mCONFIG_SYS_SUPPORTS_SH_CMT[0m
bool
config [31mCONFIG_MTK_TIMER[0m
bool "Mediatek timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_TIMER_OF[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Support for Mediatek timer driver.
config [31mCONFIG_SPRD_TIMER[0m
bool "Spreadtrum timer driver" if [31mCONFIG_EXPERT[0m
depends on [31mCONFIG_HAS_IOMEM[0m
depends on ([31mCONFIG_ARCH_SPRD[0m || [31mCONFIG_COMPILE_TEST[0m)
default [31mCONFIG_ARCH_SPRD[0m
select [31mCONFIG_TIMER_OF[0m
help
Enables support for the Spreadtrum timer driver.
config [31mCONFIG_SYS_SUPPORTS_SH_MTU2[0m
bool
config [31mCONFIG_SYS_SUPPORTS_SH_TMU[0m
bool
config [31mCONFIG_SYS_SUPPORTS_EM_STI[0m
bool
config [31mCONFIG_CLKSRC_JCORE_PIT[0m
bool "J-Core PIT timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_OF[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
This enables build of clocksource and clockevent driver for
the integrated PIT in the J-Core synthesizable, open source SoC.
config [31mCONFIG_SH_TIMER_CMT[0m
bool "Renesas CMT timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
default [31mCONFIG_SYS_SUPPORTS_SH_CMT[0m
help
This enables build of a clocksource and clockevent driver for
the Compare Match Timer (CMT) hardware available in 16/32/48-bit
variants on a wide range of Mobile and Automotive SoCs from Renesas.
config [31mCONFIG_SH_TIMER_MTU2[0m
bool "Renesas MTU2 timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
default [31mCONFIG_SYS_SUPPORTS_SH_MTU2[0m
help
This enables build of a clockevent driver for the Multi-Function
Timer Pulse Unit 2 (MTU2) hardware available on SoCs from Renesas.
This hardware comes with 16 bit-timer registers.
config [31mCONFIG_RENESAS_OSTM[0m
bool "Renesas OSTM timer driver" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables the support for the Renesas OSTM.
config [31mCONFIG_SH_TIMER_TMU[0m
bool "Renesas TMU timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
default [31mCONFIG_SYS_SUPPORTS_SH_TMU[0m
help
This enables build of a clocksource and clockevent driver for
the 32-bit Timer Unit (TMU) hardware available on a wide range
SoCs from Renesas.
config [31mCONFIG_EM_TIMER_STI[0m
bool "Renesas STI timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
default [31mCONFIG_SYS_SUPPORTS_EM_STI[0m
help
This enables build of a clocksource and clockevent driver for
the 48-bit System Timer (STI) hardware available on a SoCs
such as EMEV2 from former NEC Electronics.
config [31mCONFIG_CLKSRC_QCOM[0m
bool "Qualcomm MSM timer" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_ARM[0m
select [31mCONFIG_TIMER_OF[0m
help
This enables the clocksource and the per CPU clockevent driver for the
Qualcomm SoCs.
config [31mCONFIG_CLKSRC_VERSATILE[0m
bool "ARM Versatile (Express) reference platforms clock source" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_GENERIC_SCHED_CLOCK[0m && ![31mCONFIG_ARCH_USES_GETTIMEOFFSET[0m
select [31mCONFIG_TIMER_OF[0m
default y if [31mCONFIG_MFD_VEXPRESS_SYSREG[0m
help
This option enables clock source based on free running
counter available in the "System Registers" block of
[31mCONFIG_ARM[0m Versatile, RealView and Versatile Express reference
platforms.
config [31mCONFIG_CLKSRC_MIPS_GIC[0m
bool
depends on [31mCONFIG_MIPS_GIC[0m
select [31mCONFIG_TIMER_OF[0m
config [31mCONFIG_CLKSRC_TANGO_XTAL[0m
bool "Clocksource for Tango SoC" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_ARM[0m
select [31mCONFIG_TIMER_OF[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
This enables the clocksource for Tango SoC
config [31mCONFIG_CLKSRC_PXA[0m
bool "Clocksource for PXA or SA-11x0 platform" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
This enables OST0 support available on PXA and SA-11x0
platforms.
config [31mCONFIG_H8300_TMR8[0m
bool "Clockevent timer for the H8300 platform" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
help
This enables the 8 bits timer for the [31mCONFIG_H8300[0m platform.
config [31mCONFIG_H8300_TMR16[0m
bool "Clockevent timer for the H83069 platform" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
help
This enables the 16 bits timer for the [31mCONFIG_H8300[0m platform with the
[31mCONFIG_H83069[0m cpu.
config [31mCONFIG_H8300_TPU[0m
bool "Clocksource for the H8300 platform" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
help
This enables the clocksource for the [31mCONFIG_H8300[0m platform with the
[31mCONFIG_H8S2678[0m cpu.
config [31mCONFIG_CLKSRC_IMX_GPT[0m
bool "Clocksource using i.MX GPT" if [31mCONFIG_COMPILE_TEST[0m
depends on ([31mCONFIG_ARM[0m || [31mCONFIG_ARM64[0m) && [31mCONFIG_CLKDEV_LOOKUP[0m
select [31mCONFIG_CLKSRC_MMIO[0m
config [31mCONFIG_CLKSRC_IMX_TPM[0m
bool "Clocksource using i.MX TPM" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_ARM[0m && [31mCONFIG_CLKDEV_LOOKUP[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enable this option to use IMX Timer/[31mCONFIG_PWM[0m Module (TPM) timer as
clocksource.
config [31mCONFIG_TIMER_IMX_SYS_CTR[0m
bool "i.MX system counter timer" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_TIMER_OF[0m
help
Enable this option to use i.MX system counter timer as a
clockevent.
config [31mCONFIG_CLKSRC_ST_LPC[0m
bool "Low power clocksource found in the LPC" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_TIMER_OF[0m if [31mCONFIG_OF[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enable this option to use the Low Power controller timer
as clocksource.
config [31mCONFIG_ATCPIT100_TIMER[0m
bool "ATCPIT100 timer driver"
depends on [31mCONFIG_NDS32[0m || [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_TIMER_OF[0m
default [31mCONFIG_NDS32[0m
help
This option enables support for the Andestech ATCPIT100 timers.
config [31mCONFIG_RISCV_TIMER[0m
bool "Timer for the RISC-V platform"
depends on [31mCONFIG_GENERIC_SCHED_CLOCK[0m && [31mCONFIG_RISCV[0m
default y
select [31mCONFIG_TIMER_PROBE[0m
select [31mCONFIG_TIMER_OF[0m
help
This enables the per-hart timer built into all RISC-V systems, which
is accessed via both the SBI and the rdcycle instruction. This is
required for all RISC-V systems.
config [31mCONFIG_CSKY_MP_TIMER[0m
bool "SMP Timer for the C-SKY platform" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_CSKY[0m
select [31mCONFIG_TIMER_OF[0m
help
Say yes here to enable [31mCONFIG_C[0m-SKY [31mCONFIG_SMP[0m timer driver used for [31mCONFIG_C[0m-SKY [31mCONFIG_SMP[0m
system.
csky,mptimer is not only used in [31mCONFIG_SMP[0m system, it also could be used
single core system. It's not a mmio reg and it use mtcr/mfcr instruction.
config [31mCONFIG_GX6605S_TIMER[0m
bool "Gx6605s SOC system timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_CSKY[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_TIMER_OF[0m
help
This option enables support for gx6605s SOC's timer.
config [31mCONFIG_MILBEAUT_TIMER[0m
bool "Milbeaut timer driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_OF[0m
depends on [31mCONFIG_ARM[0m
select [31mCONFIG_TIMER_OF[0m
select [31mCONFIG_CLKSRC_MMIO[0m
help
Enables the support for Milbeaut timer driver.
config [31mCONFIG_INGENIC_TIMER[0m
bool "Clocksource/timer using the TCU in Ingenic JZ SoCs"
default [31mCONFIG_MACH_INGENIC[0m
depends on [31mCONFIG_MIPS[0m || [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_COMMON_CLK[0m
select [31mCONFIG_MFD_SYSCON[0m
select [31mCONFIG_TIMER_OF[0m
select [31mCONFIG_IRQ_DOMAIN[0m
help
Support for the timer/counter unit of the Ingenic JZ SoCs.
endmenu