# SPDX-License-Identifier: GPL-2.0 ifeq ($([31mCONFIG_ARCH_OMAP2PLUS[0m), y) obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o \ clkt_dpll.o clkt_iclk.o clkt_dflt.o \ clkctrl.o obj-$([31mCONFIG_SOC_AM33XX[0m) += $(clk-common) clk-33xx.o dpll3xxx.o \ clk-33xx-compat.o obj-$([31mCONFIG_SOC_TI81XX[0m) += $(clk-common) fapll.o clk-814x.o clk-816x.o obj-$([31mCONFIG_ARCH_OMAP2[0m) += $(clk-common) interface.o clk-2xxx.o obj-$([31mCONFIG_ARCH_OMAP3[0m) += $(clk-common) interface.o \ clk-3xxx.o dpll3xxx.o obj-$([31mCONFIG_ARCH_OMAP4[0m) += $(clk-common) clk-44xx.o \ dpll3xxx.o dpll44xx.o obj-$([31mCONFIG_SOC_OMAP5[0m) += $(clk-common) clk-54xx.o \ dpll3xxx.o dpll44xx.o obj-$([31mCONFIG_SOC_DRA7XX[0m) += $(clk-common) clk-7xx.o \ clk-dra7-atl.o dpll3xxx.o \ dpll44xx.o clk-7xx-compat.o obj-$([31mCONFIG_SOC_AM43XX[0m) += $(clk-common) dpll3xxx.o clk-43xx.o \ clk-43xx-compat.o endif # [31mCONFIG_ARCH_OMAP2PLUS[0m obj-$([31mCONFIG_COMMON_CLK_TI_ADPLL[0m) += adpll.o |