# SPDX-License-Identifier: GPL-2.0-only
#
# [31mCONFIG_FPGA[0m framework configuration
#
menuconfig [31mCONFIG_FPGA[0m
tristate "FPGA Configuration Framework"
help
Say Y here if you want support for configuring FPGAs from the
kernel. The [31mCONFIG_FPGA[0m framework adds a [31mCONFIG_FPGA[0m manager class and [31mCONFIG_FPGA[0m
manager drivers.
if [31mCONFIG_FPGA[0m
config [31mCONFIG_FPGA_MGR_SOCFPGA[0m
tristate "Altera SOCFPGA FPGA Manager"
depends on [31mCONFIG_ARCH_SOCFPGA[0m || [31mCONFIG_COMPILE_TEST[0m
help
[31mCONFIG_FPGA[0m manager driver support for Altera SOCFPGA.
config [31mCONFIG_FPGA_MGR_SOCFPGA_A10[0m
tristate "Altera SoCFPGA Arria10"
depends on [31mCONFIG_ARCH_SOCFPGA[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_REGMAP_MMIO[0m
help
[31mCONFIG_FPGA[0m manager driver support for Altera Arria10 SoCFPGA.
config [31mCONFIG_ALTERA_PR_IP_CORE[0m
tristate "Altera Partial Reconfiguration IP Core"
help
Core driver support for Altera Partial Reconfiguration IP component
config [31mCONFIG_ALTERA_PR_IP_CORE_PLAT[0m
tristate "Platform support of Altera Partial Reconfiguration IP Core"
depends on [31mCONFIG_ALTERA_PR_IP_CORE[0m && [31mCONFIG_OF[0m && [31mCONFIG_HAS_IOMEM[0m
help
Platform driver support for Altera Partial Reconfiguration IP
component
config [31mCONFIG_FPGA_MGR_ALTERA_PS_SPI[0m
tristate "Altera FPGA Passive Serial over SPI"
depends on [31mCONFIG_SPI[0m
select [31mCONFIG_BITREVERSE[0m
help
[31mCONFIG_FPGA[0m manager driver support for Altera Arria/Cyclone/Stratix
using the passive serial interface over [31mCONFIG_SPI[0m.
config [31mCONFIG_FPGA_MGR_ALTERA_CVP[0m
tristate "Altera CvP FPGA Manager"
depends on [31mCONFIG_PCI[0m
help
[31mCONFIG_FPGA[0m manager driver support for Arria-V, Cyclone-V, Stratix-V,
Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
config [31mCONFIG_FPGA_MGR_ZYNQ_FPGA[0m
tristate "Xilinx Zynq FPGA"
depends on [31mCONFIG_ARCH_ZYNQ[0m || [31mCONFIG_COMPILE_TEST[0m
help
[31mCONFIG_FPGA[0m manager driver support for Xilinx Zynq FPGAs.
config [31mCONFIG_FPGA_MGR_STRATIX10_SOC[0m
tristate "Intel Stratix10 SoC FPGA Manager"
depends on ([31mCONFIG_ARCH_STRATIX10[0m && [31mCONFIG_INTEL_STRATIX10_SERVICE[0m)
help
[31mCONFIG_FPGA[0m manager driver support for the Intel Stratix10 SoC.
config [31mCONFIG_FPGA_MGR_XILINX_SPI[0m
tristate "Xilinx Configuration over Slave Serial (SPI)"
depends on [31mCONFIG_SPI[0m
help
[31mCONFIG_FPGA[0m manager driver support for Xilinx [31mCONFIG_FPGA[0m configuration
over slave serial interface.
config [31mCONFIG_FPGA_MGR_ICE40_SPI[0m
tristate "Lattice iCE40 SPI"
depends on [31mCONFIG_OF[0m && [31mCONFIG_SPI[0m
help
[31mCONFIG_FPGA[0m manager driver support for Lattice iCE40 FPGAs over [31mCONFIG_SPI[0m.
config [31mCONFIG_FPGA_MGR_MACHXO2_SPI[0m
tristate "Lattice MachXO2 SPI"
depends on [31mCONFIG_SPI[0m
help
[31mCONFIG_FPGA[0m manager driver support for Lattice MachXO2 configuration
over slave [31mCONFIG_SPI[0m interface.
config [31mCONFIG_FPGA_MGR_TS73XX[0m
tristate "Technologic Systems TS-73xx SBC FPGA Manager"
depends on [31mCONFIG_ARCH_EP93XX[0m && [31mCONFIG_MACH_TS72XX[0m
help
[31mCONFIG_FPGA[0m manager driver support for the Altera Cyclone II [31mCONFIG_FPGA[0m
present on the TS-73xx SBC boards.
config [31mCONFIG_FPGA_BRIDGE[0m
tristate "FPGA Bridge Framework"
help
Say Y here if you want to support bridges connected between host
processors and FPGAs or between FPGAs.
config [31mCONFIG_SOCFPGA_FPGA_BRIDGE[0m
tristate "Altera SoCFPGA FPGA Bridges"
depends on [31mCONFIG_ARCH_SOCFPGA[0m && [31mCONFIG_FPGA_BRIDGE[0m
help
Say Y to enable drivers for [31mCONFIG_FPGA[0m bridges for Altera SOCFPGA
devices.
config [31mCONFIG_ALTERA_FREEZE_BRIDGE[0m
tristate "Altera FPGA Freeze Bridge"
depends on [31mCONFIG_FPGA_BRIDGE[0m && [31mCONFIG_HAS_IOMEM[0m
help
Say Y to enable drivers for Altera [31mCONFIG_FPGA[0m Freeze bridges. [31mCONFIG_A[0m
freeze bridge is a bridge that exists in the [31mCONFIG_FPGA[0m fabric to
isolate one region of the [31mCONFIG_FPGA[0m from the busses while that
region is being reprogrammed.
config [31mCONFIG_XILINX_PR_DECOUPLER[0m
tristate "Xilinx LogiCORE PR Decoupler"
depends on [31mCONFIG_FPGA_BRIDGE[0m
depends on [31mCONFIG_HAS_IOMEM[0m
help
Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
The PR Decoupler exists in the [31mCONFIG_FPGA[0m fabric to isolate one
region of the [31mCONFIG_FPGA[0m from the busses while that region is
being reprogrammed during partial reconfig.
config [31mCONFIG_FPGA_REGION[0m
tristate "FPGA Region"
depends on [31mCONFIG_FPGA_BRIDGE[0m
help
[31mCONFIG_FPGA[0m Region common code. [31mCONFIG_A[0m [31mCONFIG_FPGA[0m Region controls a [31mCONFIG_FPGA[0m Manager
and the [31mCONFIG_FPGA[0m Bridges associated with either a reconfigurable
region of an [31mCONFIG_FPGA[0m or a whole [31mCONFIG_FPGA[0m.
config [31mCONFIG_OF_FPGA_REGION[0m
tristate "FPGA Region Device Tree Overlay Support"
depends on [31mCONFIG_OF[0m && [31mCONFIG_FPGA_REGION[0m
help
Support for loading [31mCONFIG_FPGA[0m images by applying a Device Tree
overlay.
config [31mCONFIG_FPGA_DFL[0m
tristate "FPGA Device Feature List (DFL) support"
select [31mCONFIG_FPGA_BRIDGE[0m
select [31mCONFIG_FPGA_REGION[0m
help
Device Feature List (DFL) defines a feature list structure that
creates a linked list of feature headers within the MMIO space
to provide an extensible way of adding features for [31mCONFIG_FPGA[0m.
Driver can walk through the feature headers to enumerate feature
devices (e.g. [31mCONFIG_FPGA[0m Management Engine, Port and Accelerator
Function Unit) and their private features for target [31mCONFIG_FPGA[0m devices.
Select this option to enable common support for Field-Programmable
Gate Array ([31mCONFIG_FPGA[0m) solutions which implement Device Feature List.
It provides enumeration APIs and feature device infrastructure.
config [31mCONFIG_FPGA_DFL_FME[0m
tristate "FPGA DFL FME Driver"
depends on [31mCONFIG_FPGA_DFL[0m
help
The [31mCONFIG_FPGA[0m Management Engine (FME) is a feature device implemented
under Device Feature List (DFL) framework. Select this option to
enable the platform device driver for FME which implements all
[31mCONFIG_FPGA[0m platform level management features. There shall be one FME
per DFL based [31mCONFIG_FPGA[0m device.
config [31mCONFIG_FPGA_DFL_FME_MGR[0m
tristate "FPGA DFL FME Manager Driver"
depends on [31mCONFIG_FPGA_DFL_FME[0m && [31mCONFIG_HAS_IOMEM[0m
help
Say Y to enable [31mCONFIG_FPGA[0m Manager driver for [31mCONFIG_FPGA[0m Management Engine.
config [31mCONFIG_FPGA_DFL_FME_BRIDGE[0m
tristate "FPGA DFL FME Bridge Driver"
depends on [31mCONFIG_FPGA_DFL_FME[0m && [31mCONFIG_HAS_IOMEM[0m
help
Say Y to enable [31mCONFIG_FPGA[0m Bridge driver for [31mCONFIG_FPGA[0m Management Engine.
config [31mCONFIG_FPGA_DFL_FME_REGION[0m
tristate "FPGA DFL FME Region Driver"
depends on [31mCONFIG_FPGA_DFL_FME[0m && [31mCONFIG_HAS_IOMEM[0m
help
Say Y to enable [31mCONFIG_FPGA[0m Region driver for [31mCONFIG_FPGA[0m Management Engine.
config [31mCONFIG_FPGA_DFL_AFU[0m
tristate "FPGA DFL AFU Driver"
depends on [31mCONFIG_FPGA_DFL[0m
help
This is the driver for [31mCONFIG_FPGA[0m Accelerated Function Unit (AFU) which
implements AFU and Port management features. [31mCONFIG_A[0m User AFU connects
to the [31mCONFIG_FPGA[0m infrastructure via a Port. There may be more than one
Port/AFU per DFL based [31mCONFIG_FPGA[0m device.
config [31mCONFIG_FPGA_DFL_PCI[0m
tristate "FPGA DFL PCIe Device Driver"
depends on [31mCONFIG_PCI[0m && [31mCONFIG_FPGA_DFL[0m
help
Select this option to enable PCIe driver for PCIe-based
Field-Programmable Gate Array ([31mCONFIG_FPGA[0m) solutions which implement
the Device Feature List (DFL). This driver provides interfaces
for userspace applications to configure, enumerate, open and access
[31mCONFIG_FPGA[0m accelerators on the [31mCONFIG_FPGA[0m DFL devices, enables system level
management functions such as [31mCONFIG_FPGA[0m partial reconfiguration, power
management and virtualization with DFL framework and DFL feature
device drivers.
To compile this as a module, choose [31mCONFIG_M[0m here.
config [31mCONFIG_FPGA_MGR_ZYNQMP_FPGA[0m
tristate "Xilinx ZynqMP FPGA"
depends on [31mCONFIG_ARCH_ZYNQMP[0m || [31mCONFIG_COMPILE_TEST[0m
help
[31mCONFIG_FPGA[0m manager driver support for Xilinx ZynqMP FPGAs.
This driver uses the processor configuration port(PCAP)
to configure the programmable logic(PL) through PS
on ZynqMP SoC.
endif # [31mCONFIG_FPGA[0m