# SPDX-License-Identifier: GPL-2.0-only
#
# Coresight configuration
#
menuconfig [31mCONFIG_CORESIGHT[0m
bool "CoreSight Tracing Support"
depends on [31mCONFIG_OF[0m || [31mCONFIG_ACPI[0m
select [31mCONFIG_ARM_AMBA[0m
select [31mCONFIG_PERF_EVENTS[0m
help
This framework provides a kernel interface for the CoreSight debug
and trace drivers to register themselves with. It's intended to build
a topological view of the CoreSight components based on a DT
specification and configure the right series of components when a
trace source gets enabled.
if [31mCONFIG_CORESIGHT[0m
config [31mCONFIG_CORESIGHT_LINKS_AND_SINKS[0m
bool "CoreSight Link and Sink drivers"
help
This enables support for CoreSight link and sink drivers that are
responsible for transporting and collecting the trace data
respectively. Link and sinks are dynamically aggregated with a trace
entity at run time to form a complete trace path.
config [31mCONFIG_CORESIGHT_LINK_AND_SINK_TMC[0m
bool "Coresight generic TMC driver"
depends on [31mCONFIG_CORESIGHT_LINKS_AND_SINKS[0m
help
This enables support for the Trace Memory Controller driver.
Depending on its configuration the device can act as a link (embedded
trace router - ETR) or sink (embedded trace FIFO). The driver
complies with the generic implementation of the component without
special enhancement or added features.
config [31mCONFIG_CORESIGHT_CATU[0m
bool "Coresight Address Translation Unit (CATU) driver"
depends on [31mCONFIG_CORESIGHT_LINK_AND_SINK_TMC[0m
help
Enable support for the Coresight Address Translation Unit (CATU).
CATU supports a scatter gather table of 4K pages, with forward/backward
lookup. CATU helps TMC ETR to use a large physically non-contiguous trace
buffer by translating the addresses used by ETR to the physical address
by looking up the provided table. CATU can also be used in pass-through
mode where the address is not translated.
config [31mCONFIG_CORESIGHT_SINK_TPIU[0m
bool "Coresight generic TPIU driver"
depends on [31mCONFIG_CORESIGHT_LINKS_AND_SINKS[0m
help
This enables support for the Trace Port Interface Unit driver,
responsible for bridging the gap between the on-chip coresight
components and a trace for bridging the gap between the on-chip
coresight components and a trace port collection engine, typically
connected to an external host for use case capturing more traces than
the on-board coresight memory can handle.
config [31mCONFIG_CORESIGHT_SINK_ETBV10[0m
bool "Coresight ETBv1.0 driver"
depends on [31mCONFIG_CORESIGHT_LINKS_AND_SINKS[0m
help
This enables support for the Embedded Trace Buffer version 1.0 driver
that complies with the generic implementation of the component without
special enhancement or added features.
config [31mCONFIG_CORESIGHT_SOURCE_ETM3X[0m
bool "CoreSight Embedded Trace Macrocell 3.x driver"
depends on ![31mCONFIG_ARM64[0m
select [31mCONFIG_CORESIGHT_LINKS_AND_SINKS[0m
help
This driver provides support for processor ETM3.x and PTM1.x modules,
which allows tracing the instructions that a processor is executing
This is primarily useful for instruction level tracing. Depending
the ETM version data tracing may also be available.
config [31mCONFIG_CORESIGHT_SOURCE_ETM4X[0m
bool "CoreSight Embedded Trace Macrocell 4.x driver"
depends on [31mCONFIG_ARM64[0m
select [31mCONFIG_CORESIGHT_LINKS_AND_SINKS[0m
select [31mCONFIG_PID_IN_CONTEXTIDR[0m
help
This driver provides support for the ETM4.x tracer module, tracing the
instructions that a processor is executing. This is primarily useful
for instruction level tracing. Depending on the implemented version
data tracing may also be available.
config [31mCONFIG_CORESIGHT_STM[0m
bool "CoreSight System Trace Macrocell driver"
depends on ([31mCONFIG_ARM[0m && !([31mCONFIG_CPU_32v3[0m || [31mCONFIG_CPU_32v4[0m || [31mCONFIG_CPU_32v4T[0m)) || [31mCONFIG_ARM64[0m
select [31mCONFIG_CORESIGHT_LINKS_AND_SINKS[0m
select [31mCONFIG_STM[0m
help
This driver provides support for hardware assisted software
instrumentation based tracing. This is primarily used for
logging useful software events or data coming from various entities
in the system, possibly running different OSs
config [31mCONFIG_CORESIGHT_CPU_DEBUG[0m
tristate "CoreSight CPU Debug driver"
depends on [31mCONFIG_ARM[0m || [31mCONFIG_ARM64[0m
depends on [31mCONFIG_DEBUG_FS[0m
help
This driver provides support for coresight debugging module. This
is primarily used to dump sample-based profiling registers when
system triggers panic, the driver will parse context registers so
can quickly get to know program counter (PC), secure state,
exception level, etc. Before use debugging functionality, platform
needs to ensure the clock domain and power domain are enabled
properly, please refer Documentation/trace/coresight-cpu-debug.rst
for detailed description and the example for usage.
endif