# SPDX-License-Identifier: GPL-2.0
# Intel pin control drivers
if ([31mCONFIG_X86[0m || [31mCONFIG_COMPILE_TEST[0m)
config [31mCONFIG_PINCTRL_BAYTRAIL[0m
bool "Intel Baytrail GPIO pin control"
depends on [31mCONFIG_ACPI[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_GPIOLIB_IRQCHIP[0m
select [31mCONFIG_PINMUX[0m
select [31mCONFIG_PINCONF[0m
select [31mCONFIG_GENERIC_PINCONF[0m
help
driver for memory mapped GPIO functionality on Intel Baytrail
platforms. Supports 3 banks with 102, 28 and 44 gpios.
Most pins are usually muxed to some other functionality by firmware,
so only a small amount is available for gpio use.
Requires [31mCONFIG_ACPI[0m device enumeration code to set up a platform device.
config [31mCONFIG_PINCTRL_CHERRYVIEW[0m
tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
depends on [31mCONFIG_ACPI[0m
select [31mCONFIG_PINMUX[0m
select [31mCONFIG_PINCONF[0m
select [31mCONFIG_GENERIC_PINCONF[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_GPIOLIB_IRQCHIP[0m
help
Cherryview/Braswell pinctrl driver provides an interface that
allows configuring of SoC pins and using them as GPIOs.
config [31mCONFIG_PINCTRL_MERRIFIELD[0m
tristate "Intel Merrifield pinctrl driver"
depends on [31mCONFIG_X86_INTEL_MID[0m
select [31mCONFIG_PINMUX[0m
select [31mCONFIG_PINCONF[0m
select [31mCONFIG_GENERIC_PINCONF[0m
help
Merrifield Family-Level Interface Shim (FLIS) driver provides an
interface that allows configuring of SoC pins and using them as
GPIOs.
config [31mCONFIG_PINCTRL_INTEL[0m
tristate
select [31mCONFIG_PINMUX[0m
select [31mCONFIG_PINCONF[0m
select [31mCONFIG_GENERIC_PINCONF[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_GPIOLIB_IRQCHIP[0m
config [31mCONFIG_PINCTRL_BROXTON[0m
tristate "Intel Broxton pinctrl and GPIO driver"
depends on [31mCONFIG_ACPI[0m
select [31mCONFIG_PINCTRL_INTEL[0m
help
Broxton pinctrl driver provides an interface that allows
configuring of SoC pins and using them as GPIOs.
config [31mCONFIG_PINCTRL_CANNONLAKE[0m
tristate "Intel Cannon Lake PCH pinctrl and GPIO driver"
depends on [31mCONFIG_ACPI[0m
select [31mCONFIG_PINCTRL_INTEL[0m
help
This pinctrl driver provides an interface that allows configuring
of Intel Cannon Lake PCH pins and using them as GPIOs.
config [31mCONFIG_PINCTRL_CEDARFORK[0m
tristate "Intel Cedar Fork pinctrl and GPIO driver"
depends on [31mCONFIG_ACPI[0m
select [31mCONFIG_PINCTRL_INTEL[0m
help
This pinctrl driver provides an interface that allows configuring
of Intel Cedar Fork PCH pins and using them as GPIOs.
config [31mCONFIG_PINCTRL_DENVERTON[0m
tristate "Intel Denverton pinctrl and GPIO driver"
depends on [31mCONFIG_ACPI[0m
select [31mCONFIG_PINCTRL_INTEL[0m
help
This pinctrl driver provides an interface that allows configuring
of Intel Denverton SoC pins and using them as GPIOs.
config [31mCONFIG_PINCTRL_GEMINILAKE[0m
tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
depends on [31mCONFIG_ACPI[0m
select [31mCONFIG_PINCTRL_INTEL[0m
help
This pinctrl driver provides an interface that allows configuring
of Intel Gemini Lake SoC pins and using them as GPIOs.
config [31mCONFIG_PINCTRL_ICELAKE[0m
tristate "Intel Ice Lake PCH pinctrl and GPIO driver"
depends on [31mCONFIG_ACPI[0m
select [31mCONFIG_PINCTRL_INTEL[0m
help
This pinctrl driver provides an interface that allows configuring
of Intel Ice Lake PCH pins and using them as GPIOs.
config [31mCONFIG_PINCTRL_LEWISBURG[0m
tristate "Intel Lewisburg pinctrl and GPIO driver"
depends on [31mCONFIG_ACPI[0m
select [31mCONFIG_PINCTRL_INTEL[0m
help
This pinctrl driver provides an interface that allows configuring
of Intel Lewisburg pins and using them as GPIOs.
config [31mCONFIG_PINCTRL_SUNRISEPOINT[0m
tristate "Intel Sunrisepoint pinctrl and GPIO driver"
depends on [31mCONFIG_ACPI[0m
select [31mCONFIG_PINCTRL_INTEL[0m
help
Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
provides an interface that allows configuring of PCH pins and
using them as GPIOs.
endif