# SPDX-License-Identifier: GPL-2.0 config [31mCONFIG_VIDEO_ALLEGRO_DVT[0m tristate "Allegro DVT Video IP Core" depends on [31mCONFIG_VIDEO_DEV[0m && [31mCONFIG_VIDEO_V4L2[0m depends on [31mCONFIG_ARCH_ZYNQMP[0m || [31mCONFIG_COMPILE_TEST[0m select [31mCONFIG_V4L2_MEM2MEM_DEV[0m select [31mCONFIG_VIDEOBUF2_DMA_CONTIG[0m select [31mCONFIG_REGMAP[0m select [31mCONFIG_REGMAP_MMIO[0m help Support for the encoder video IP core by Allegro DVT. This core is found for example on the Xilinx ZynqMP SoC in the EV family and is called VCU in the reference manual. To compile this driver as a module, choose [31mCONFIG_M[0m here: the module will be called allegro. |