Allwinner Memory Bus (MBUS) controller

The MBUS controller drives the MBUS that other devices in the SoC will
use to perform DMA. It also has a register interface that allows to
monitor and control the bandwidth and priorities for masters on that
bus.

Required properties:
 - compatible: Must be one of:
	- allwinner,sun5i-a13-mbus
 - reg: Offset and length of the register set for the controller
 - clocks: phandle to the clock driving the controller
 - dma-ranges: See section 2.3.9 of the DeviceTree Specification
 - #interconnect-cells: Must be one, with the argument being the MBUS
   port ID

Each device having to perform their DMA through the MBUS must have the
interconnects and interconnect-names properties set to the MBUS
controller and with "dma-mem" as the interconnect name.

Example:

mbus: dram-controller@1c01000 {
	compatible = "allwinner,sun5i-a13-mbus";
	reg = <0x01c01000 0x1000>;
	clocks = <&ccu CLK_MBUS>;
	dma-ranges = <0x00000000 0x40000000 0x20000000>;
	#interconnect-cells = <1>;
};

fe0: display-frontend@1e00000 {
	compatible = "allwinner,sun5i-a13-display-frontend";
	...
	interconnects = <&mbus 19>;
	interconnect-names = "dma-mem";
};