# SPDX-License-Identifier: GPL-2.0
comment "Processor Type"
# Select CPU types depending on the architecture selected. This selects
# which CPUs we support in the kernel image, and the compiler instruction
# optimiser behaviour.
# ARM7TDMI
config [31mCONFIG_CPU_ARM7TDMI[0m
bool
depends on ![31mCONFIG_MMU[0m
select [31mCONFIG_CPU_32v4T[0m
select [31mCONFIG_CPU_ABRT_LV4T[0m
select [31mCONFIG_CPU_CACHE_V4[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
help
[31mCONFIG_A[0m 32-bit RISC microprocessor based on the ARM7 processor core
which has no memory control unit and cache.
Say Y if you want support for the ARM7TDMI processor.
Otherwise, say N.
# ARM720T
config [31mCONFIG_CPU_ARM720T[0m
bool
select [31mCONFIG_CPU_32v4T[0m
select [31mCONFIG_CPU_ABRT_LV4T[0m
select [31mCONFIG_CPU_CACHE_V4[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_COPY_V4WT[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V4WT[0m if [31mCONFIG_MMU[0m
help
[31mCONFIG_A[0m 32-bit RISC processor with 8kByte Cache, Write Buffer and
[31mCONFIG_MMU[0m built around an ARM7TDMI core.
Say Y if you want support for the ARM720T processor.
Otherwise, say N.
# ARM740T
config [31mCONFIG_CPU_ARM740T[0m
bool
depends on ![31mCONFIG_MMU[0m
select [31mCONFIG_CPU_32v4T[0m
select [31mCONFIG_CPU_ABRT_LV4T[0m
select [31mCONFIG_CPU_CACHE_V4[0m
select [31mCONFIG_CPU_CP15_MPU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
help
[31mCONFIG_A[0m 32-bit RISC processor with 8KB cache or 4KB variants,
write buffer and [31mCONFIG_MPU[0m(Protection Unit) built around
an ARM7TDMI core.
Say Y if you want support for the ARM740T processor.
Otherwise, say N.
# ARM9TDMI
config [31mCONFIG_CPU_ARM9TDMI[0m
bool
depends on ![31mCONFIG_MMU[0m
select [31mCONFIG_CPU_32v4T[0m
select [31mCONFIG_CPU_ABRT_NOMMU[0m
select [31mCONFIG_CPU_CACHE_V4[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
help
[31mCONFIG_A[0m 32-bit RISC microprocessor based on the ARM9 processor core
which has no memory control unit and cache.
Say Y if you want support for the ARM9TDMI processor.
Otherwise, say N.
# ARM920T
config [31mCONFIG_CPU_ARM920T[0m
bool
select [31mCONFIG_CPU_32v4T[0m
select [31mCONFIG_CPU_ABRT_EV4T[0m
select [31mCONFIG_CPU_CACHE_V4WT[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_COPY_V4WB[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V4WBI[0m if [31mCONFIG_MMU[0m
help
The ARM920T is licensed to be produced by numerous vendors,
and is used in the Cirrus EP93xx and the Samsung S3C2410.
Say Y if you want support for the ARM920T processor.
Otherwise, say N.
# ARM922T
config [31mCONFIG_CPU_ARM922T[0m
bool
select [31mCONFIG_CPU_32v4T[0m
select [31mCONFIG_CPU_ABRT_EV4T[0m
select [31mCONFIG_CPU_CACHE_V4WT[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_COPY_V4WB[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V4WBI[0m if [31mCONFIG_MMU[0m
help
The ARM922T is a version of the ARM920T, but with smaller
instruction and data caches. It is used in Altera's
Excalibur XA device family and the [31mCONFIG_ARM[0m Integrator.
Say Y if you want support for the ARM922T processor.
Otherwise, say N.
# ARM925T
config [31mCONFIG_CPU_ARM925T[0m
bool
select [31mCONFIG_CPU_32v4T[0m
select [31mCONFIG_CPU_ABRT_EV4T[0m
select [31mCONFIG_CPU_CACHE_V4WT[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_COPY_V4WB[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V4WBI[0m if [31mCONFIG_MMU[0m
help
The ARM925T is a mix between the ARM920T and ARM926T, but with
different instruction and data caches. It is used in TI's OMAP
device family.
Say Y if you want support for the ARM925T processor.
Otherwise, say N.
# ARM926T
config [31mCONFIG_CPU_ARM926T[0m
bool
select [31mCONFIG_CPU_32v5[0m
select [31mCONFIG_CPU_ABRT_EV5TJ[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_COPY_V4WB[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V4WBI[0m if [31mCONFIG_MMU[0m
help
This is a variant of the ARM920. It has slightly different
instruction sequences for cache and TLB operations. Curiously,
there is no documentation on it at the [31mCONFIG_ARM[0m corporate website.
Say Y if you want support for the ARM926T processor.
Otherwise, say N.
# FA526
config [31mCONFIG_CPU_FA526[0m
bool
select [31mCONFIG_CPU_32v4[0m
select [31mCONFIG_CPU_ABRT_EV4[0m
select [31mCONFIG_CPU_CACHE_FA[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_COPY_FA[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_TLB_FA[0m if [31mCONFIG_MMU[0m
help
The FA526 is a version of the ARMv4 compatible processor with
Branch Target Buffer, Unified TLB and cache line size 16.
Say Y if you want support for the FA526 processor.
Otherwise, say N.
# ARM940T
config [31mCONFIG_CPU_ARM940T[0m
bool
depends on ![31mCONFIG_MMU[0m
select [31mCONFIG_CPU_32v4T[0m
select [31mCONFIG_CPU_ABRT_NOMMU[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_CP15_MPU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
help
ARM940T is a member of the ARM9TDMI family of general-
purpose microprocessors with [31mCONFIG_MPU[0m and separate 4KB
instruction and 4KB data cases, each with a 4-word line
length.
Say Y if you want support for the ARM940T processor.
Otherwise, say N.
# ARM946E-S
config [31mCONFIG_CPU_ARM946E[0m
bool
depends on ![31mCONFIG_MMU[0m
select [31mCONFIG_CPU_32v5[0m
select [31mCONFIG_CPU_ABRT_NOMMU[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_CP15_MPU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
help
ARM946E-S is a member of the ARM9E-S family of high-
performance, 32-bit system-on-chip processor solutions.
The TCM and ARMv5TE 32-bit instruction set is supported.
Say Y if you want support for the ARM946E-S processor.
Otherwise, say N.
# ARM1020 - needs validating
config [31mCONFIG_CPU_ARM1020[0m
bool
select [31mCONFIG_CPU_32v5[0m
select [31mCONFIG_CPU_ABRT_EV4T[0m
select [31mCONFIG_CPU_CACHE_V4WT[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_COPY_V4WB[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V4WBI[0m if [31mCONFIG_MMU[0m
help
The ARM1020 is the 32K cached version of the ARM10 processor,
with an addition of a floating-point unit.
Say Y if you want support for the ARM1020 processor.
Otherwise, say N.
# ARM1020E - needs validating
config [31mCONFIG_CPU_ARM1020E[0m
bool
depends on n
select [31mCONFIG_CPU_32v5[0m
select [31mCONFIG_CPU_ABRT_EV4T[0m
select [31mCONFIG_CPU_CACHE_V4WT[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_COPY_V4WB[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V4WBI[0m if [31mCONFIG_MMU[0m
# ARM1022E
config [31mCONFIG_CPU_ARM1022[0m
bool
select [31mCONFIG_CPU_32v5[0m
select [31mCONFIG_CPU_ABRT_EV4T[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_COPY_V4WB[0m if [31mCONFIG_MMU[0m # can probably do better
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V4WBI[0m if [31mCONFIG_MMU[0m
help
The ARM1022E is an implementation of the ARMv5TE architecture
based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
embedded trace macrocell, and a floating-point unit.
Say Y if you want support for the ARM1022E processor.
Otherwise, say N.
# ARM1026EJ-S
config [31mCONFIG_CPU_ARM1026[0m
bool
select [31mCONFIG_CPU_32v5[0m
select [31mCONFIG_CPU_ABRT_EV5T[0m # But need Jazelle, but EV5TJ ignores bit 10
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_COPY_V4WB[0m if [31mCONFIG_MMU[0m # can probably do better
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V4WBI[0m if [31mCONFIG_MMU[0m
help
The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
based upon the ARM10 integer core.
Say Y if you want support for the ARM1026EJ-S processor.
Otherwise, say N.
# SA110
config [31mCONFIG_CPU_SA110[0m
bool
select [31mCONFIG_CPU_32v3[0m if [31mCONFIG_ARCH_RPC[0m
select [31mCONFIG_CPU_32v4[0m if ![31mCONFIG_ARCH_RPC[0m
select [31mCONFIG_CPU_ABRT_EV4[0m
select [31mCONFIG_CPU_CACHE_V4WB[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_COPY_V4WB[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_TLB_V4WB[0m if [31mCONFIG_MMU[0m
help
The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
is available at five speeds ranging from 100 MHz to 233 MHz.
More information is available at
<http://developer.intel.com/design/strong/sa110.htm>.
Say Y if you want support for the SA-110 processor.
Otherwise, say N.
# SA1100
config [31mCONFIG_CPU_SA1100[0m
bool
select [31mCONFIG_CPU_32v4[0m
select [31mCONFIG_CPU_ABRT_EV4[0m
select [31mCONFIG_CPU_CACHE_V4WB[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_TLB_V4WB[0m if [31mCONFIG_MMU[0m
# XScale
config [31mCONFIG_CPU_XSCALE[0m
bool
select [31mCONFIG_CPU_32v5[0m
select [31mCONFIG_CPU_ABRT_EV5T[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V4WBI[0m if [31mCONFIG_MMU[0m
# XScale Core Version 3
config [31mCONFIG_CPU_XSC3[0m
bool
select [31mCONFIG_CPU_32v5[0m
select [31mCONFIG_CPU_ABRT_EV5T[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V4WBI[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_IO_36[0m
# Marvell PJ1 (Mohawk)
config [31mCONFIG_CPU_MOHAWK[0m
bool
select [31mCONFIG_CPU_32v5[0m
select [31mCONFIG_CPU_ABRT_EV5T[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_COPY_V4WB[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V4WBI[0m if [31mCONFIG_MMU[0m
# Feroceon
config [31mCONFIG_CPU_FEROCEON[0m
bool
select [31mCONFIG_CPU_32v5[0m
select [31mCONFIG_CPU_ABRT_EV5T[0m
select [31mCONFIG_CPU_CACHE_VIVT[0m
select [31mCONFIG_CPU_COPY_FEROCEON[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_FEROCEON[0m if [31mCONFIG_MMU[0m
config [31mCONFIG_CPU_FEROCEON_OLD_ID[0m
bool "Accept early Feroceon cores with an ARM926 ID"
depends on [31mCONFIG_CPU_FEROCEON[0m && ![31mCONFIG_CPU_ARM926T[0m
default y
help
This enables the usage of some old Feroceon cores
for which the CPU ID is equal to the ARM926 ID.
Relevant for Feroceon-1850 and early Feroceon-2850.
# Marvell PJ4
config [31mCONFIG_CPU_PJ4[0m
bool
select [31mCONFIG_ARM_THUMBEE[0m
select [31mCONFIG_CPU_V7[0m
config [31mCONFIG_CPU_PJ4B[0m
bool
select [31mCONFIG_CPU_V7[0m
# ARMv6
config [31mCONFIG_CPU_V6[0m
bool
select [31mCONFIG_CPU_32v6[0m
select [31mCONFIG_CPU_ABRT_EV6[0m
select [31mCONFIG_CPU_CACHE_V6[0m
select [31mCONFIG_CPU_CACHE_VIPT[0m
select [31mCONFIG_CPU_COPY_V6[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_HAS_ASID[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_PABRT_V6[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V6[0m if [31mCONFIG_MMU[0m
# ARMv6k
config [31mCONFIG_CPU_V6K[0m
bool
select [31mCONFIG_CPU_32v6[0m
select [31mCONFIG_CPU_32v6K[0m
select [31mCONFIG_CPU_ABRT_EV6[0m
select [31mCONFIG_CPU_CACHE_V6[0m
select [31mCONFIG_CPU_CACHE_VIPT[0m
select [31mCONFIG_CPU_COPY_V6[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MMU[0m
select [31mCONFIG_CPU_HAS_ASID[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_PABRT_V6[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V6[0m if [31mCONFIG_MMU[0m
# ARMv7
config [31mCONFIG_CPU_V7[0m
bool
select [31mCONFIG_CPU_32v6K[0m
select [31mCONFIG_CPU_32v7[0m
select [31mCONFIG_CPU_ABRT_EV7[0m
select [31mCONFIG_CPU_CACHE_V7[0m
select [31mCONFIG_CPU_CACHE_VIPT[0m
select [31mCONFIG_CPU_COPY_V6[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MMU[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_CP15_MPU[0m if ![31mCONFIG_MMU[0m
select [31mCONFIG_CPU_HAS_ASID[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_PABRT_V7[0m
select [31mCONFIG_CPU_SPECTRE[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
select [31mCONFIG_CPU_TLB_V7[0m if [31mCONFIG_MMU[0m
# ARMv7M
config [31mCONFIG_CPU_V7M[0m
bool
select [31mCONFIG_CPU_32v7M[0m
select [31mCONFIG_CPU_ABRT_NOMMU[0m
select [31mCONFIG_CPU_CACHE_V7M[0m
select [31mCONFIG_CPU_CACHE_NOP[0m
select [31mCONFIG_CPU_PABRT_LEGACY[0m
select [31mCONFIG_CPU_THUMBONLY[0m
config [31mCONFIG_CPU_THUMBONLY[0m
bool
select [31mCONFIG_CPU_THUMB_CAPABLE[0m
# There are no CPUs available with [31mCONFIG_MMU[0m that don't implement an [31mCONFIG_ARM[0m [31mCONFIG_ISA[0m:
depends on ![31mCONFIG_MMU[0m
help
Select this if your CPU doesn't support the 32 bit [31mCONFIG_ARM[0m instructions.
config [31mCONFIG_CPU_THUMB_CAPABLE[0m
bool
help
Select this if your CPU can support Thumb mode.
# Figure out what processor architecture version we should be using.
# This defines the compiler instruction set which depends on the machine type.
config [31mCONFIG_CPU_32v3[0m
bool
select [31mCONFIG_CPU_USE_DOMAINS[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_NEED_KUSER_HELPERS[0m
select [31mCONFIG_TLS_REG_EMUL[0m if [31mCONFIG_SMP[0m || ![31mCONFIG_MMU[0m
select [31mCONFIG_CPU_NO_EFFICIENT_FFS[0m
config [31mCONFIG_CPU_32v4[0m
bool
select [31mCONFIG_CPU_USE_DOMAINS[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_NEED_KUSER_HELPERS[0m
select [31mCONFIG_TLS_REG_EMUL[0m if [31mCONFIG_SMP[0m || ![31mCONFIG_MMU[0m
select [31mCONFIG_CPU_NO_EFFICIENT_FFS[0m
config [31mCONFIG_CPU_32v4T[0m
bool
select [31mCONFIG_CPU_USE_DOMAINS[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_NEED_KUSER_HELPERS[0m
select [31mCONFIG_TLS_REG_EMUL[0m if [31mCONFIG_SMP[0m || ![31mCONFIG_MMU[0m
select [31mCONFIG_CPU_NO_EFFICIENT_FFS[0m
config [31mCONFIG_CPU_32v5[0m
bool
select [31mCONFIG_CPU_USE_DOMAINS[0m if [31mCONFIG_MMU[0m
select [31mCONFIG_NEED_KUSER_HELPERS[0m
select [31mCONFIG_TLS_REG_EMUL[0m if [31mCONFIG_SMP[0m || ![31mCONFIG_MMU[0m
config [31mCONFIG_CPU_32v6[0m
bool
select [31mCONFIG_TLS_REG_EMUL[0m if ![31mCONFIG_CPU_32v6K[0m && ![31mCONFIG_MMU[0m
config [31mCONFIG_CPU_32v6K[0m
bool
config [31mCONFIG_CPU_32v7[0m
bool
config [31mCONFIG_CPU_32v7M[0m
bool
# The abort model
config [31mCONFIG_CPU_ABRT_NOMMU[0m
bool
config [31mCONFIG_CPU_ABRT_EV4[0m
bool
config [31mCONFIG_CPU_ABRT_EV4T[0m
bool
config [31mCONFIG_CPU_ABRT_LV4T[0m
bool
config [31mCONFIG_CPU_ABRT_EV5T[0m
bool
config [31mCONFIG_CPU_ABRT_EV5TJ[0m
bool
config [31mCONFIG_CPU_ABRT_EV6[0m
bool
config [31mCONFIG_CPU_ABRT_EV7[0m
bool
config [31mCONFIG_CPU_PABRT_LEGACY[0m
bool
config [31mCONFIG_CPU_PABRT_V6[0m
bool
config [31mCONFIG_CPU_PABRT_V7[0m
bool
# The cache model
config [31mCONFIG_CPU_CACHE_V4[0m
bool
config [31mCONFIG_CPU_CACHE_V4WT[0m
bool
config [31mCONFIG_CPU_CACHE_V4WB[0m
bool
config [31mCONFIG_CPU_CACHE_V6[0m
bool
config [31mCONFIG_CPU_CACHE_V7[0m
bool
config [31mCONFIG_CPU_CACHE_NOP[0m
bool
config [31mCONFIG_CPU_CACHE_VIVT[0m
bool
config [31mCONFIG_CPU_CACHE_VIPT[0m
bool
config [31mCONFIG_CPU_CACHE_FA[0m
bool
config [31mCONFIG_CPU_CACHE_V7M[0m
bool
if [31mCONFIG_MMU[0m
# The copy-page model
config [31mCONFIG_CPU_COPY_V4WT[0m
bool
config [31mCONFIG_CPU_COPY_V4WB[0m
bool
config [31mCONFIG_CPU_COPY_FEROCEON[0m
bool
config [31mCONFIG_CPU_COPY_FA[0m
bool
config [31mCONFIG_CPU_COPY_V6[0m
bool
# This selects the TLB model
config [31mCONFIG_CPU_TLB_V4WT[0m
bool
help
[31mCONFIG_ARM[0m Architecture Version 4 TLB with writethrough cache.
config [31mCONFIG_CPU_TLB_V4WB[0m
bool
help
[31mCONFIG_ARM[0m Architecture Version 4 TLB with writeback cache.
config [31mCONFIG_CPU_TLB_V4WBI[0m
bool
help
[31mCONFIG_ARM[0m Architecture Version 4 TLB with writeback cache and invalidate
instruction cache entry.
config [31mCONFIG_CPU_TLB_FEROCEON[0m
bool
help
Feroceon TLB (v4wbi with non-outer-cachable page table walks).
config [31mCONFIG_CPU_TLB_FA[0m
bool
help
Faraday [31mCONFIG_ARM[0m FA526 architecture, unified TLB with writeback cache
and invalidate instruction cache entry. Branch target buffer is
also supported.
config [31mCONFIG_CPU_TLB_V6[0m
bool
config [31mCONFIG_CPU_TLB_V7[0m
bool
config [31mCONFIG_VERIFY_PERMISSION_FAULT[0m
bool
endif
config [31mCONFIG_CPU_HAS_ASID[0m
bool
help
This indicates whether the CPU has the ASID register; used to
tag TLB and possibly cache entries.
config [31mCONFIG_CPU_CP15[0m
bool
help
Processor has the CP15 register.
config [31mCONFIG_CPU_CP15_MMU[0m
bool
select [31mCONFIG_CPU_CP15[0m
help
Processor has the CP15 register, which has [31mCONFIG_MMU[0m related registers.
config [31mCONFIG_CPU_CP15_MPU[0m
bool
select [31mCONFIG_CPU_CP15[0m
help
Processor has the CP15 register, which has [31mCONFIG_MPU[0m related registers.
config [31mCONFIG_CPU_USE_DOMAINS[0m
bool
help
This option enables or disables the use of domain switching
via the set_fs() function.
config [31mCONFIG_CPU_V7M_NUM_IRQ[0m
int "Number of external interrupts connected to the NVIC"
depends on [31mCONFIG_CPU_V7M[0m
default 90 if [31mCONFIG_ARCH_STM32[0m
default 38 if [31mCONFIG_ARCH_EFM32[0m
default 112 if [31mCONFIG_SOC_VF610[0m
default 240
help
This option indicates the number of interrupts connected to the NVIC.
The value can be larger than the real number of interrupts supported
by the system, but must not be lower.
The default value is 240, corresponding to the maximum number of
interrupts supported by the NVIC on Cortex-[31mCONFIG_M[0m family.
If unsure, keep default value.
#
# CPU supports 36-bit I/O
#
config [31mCONFIG_IO_36[0m
bool
comment "Processor Features"
config [31mCONFIG_ARM_LPAE[0m
bool "Support for the Large Physical Address Extension"
depends on [31mCONFIG_MMU[0m && [31mCONFIG_CPU_32v7[0m && ![31mCONFIG_CPU_32v6[0m && ![31mCONFIG_CPU_32v5[0m && \
![31mCONFIG_CPU_32v4[0m && ![31mCONFIG_CPU_32v3[0m
select [31mCONFIG_PHYS_ADDR_T_64BIT[0m
select [31mCONFIG_SWIOTLB[0m
help
Say Y if you have an ARMv7 processor supporting the LPAE page
table format and you would like to access memory beyond the
4GB limit. The resulting kernel image will not run on
processors without the LPA extension.
If unsure, say N.
config [31mCONFIG_ARM_PV_FIXUP[0m
def_bool y
depends on [31mCONFIG_ARM_LPAE[0m && [31mCONFIG_ARM_PATCH_PHYS_VIRT[0m && [31mCONFIG_ARCH_KEYSTONE[0m
config [31mCONFIG_ARM_THUMB[0m
bool "Support Thumb user binaries" if ![31mCONFIG_CPU_THUMBONLY[0m && [31mCONFIG_EXPERT[0m
depends on [31mCONFIG_CPU_THUMB_CAPABLE[0m
default y
help
Say Y if you want to include kernel support for running user space
Thumb binaries.
The Thumb instruction set is a compressed form of the standard [31mCONFIG_ARM[0m
instruction set resulting in smaller binaries at the expense of
slightly less efficient code.
If this option is disabled, and you run userspace that switches to
Thumb mode, signal handling will not work correctly, resulting in
segmentation faults or illegal instruction aborts.
If you don't know what this all is, saying Y is a safe choice.
config [31mCONFIG_ARM_THUMBEE[0m
bool "Enable ThumbEE CPU extension"
depends on [31mCONFIG_CPU_V7[0m
help
Say Y here if you have a CPU with the ThumbEE extension and code to
make use of it. Say N for code that can run on CPUs without ThumbEE.
config [31mCONFIG_ARM_VIRT_EXT[0m
bool
default y if [31mCONFIG_CPU_V7[0m
help
Enable the kernel to make use of the [31mCONFIG_ARM[0m Virtualization
Extensions to install hypervisors without run-time firmware
assistance.
[31mCONFIG_A[0m compliant bootloader is required in order to make maximum
use of this feature. Refer to Documentation/arm/booting.rst for
details.
config [31mCONFIG_SWP_EMULATE[0m
bool "Emulate SWP/SWPB instructions" if ![31mCONFIG_SMP[0m
depends on [31mCONFIG_CPU_V7[0m
default y if [31mCONFIG_SMP[0m
select [31mCONFIG_HAVE_PROC_CPU[0m if [31mCONFIG_PROC_FS[0m
help
ARMv6 architecture deprecates use of the SWP/SWPB instructions.
ARMv7 multiprocessing extensions introduce the ability to disable
these instructions, triggering an undefined instruction exception
when executed. Say Y here to enable software emulation of these
instructions for userspace (not kernel) using LDREX/STREX.
Also creates /proc/cpu/swp_emulation for statistics.
In some older versions of glibc [<=2.8] SWP is used during futex
trylock() operations with the assumption that the code will not
be preempted. This invalid assumption may be more likely to fail
with SWP emulation enabled, leading to deadlock of the user
application.
NOTE: when accessing uncached shared regions, LDREX/STREX rely
on an external transaction monitoring block called a global
monitor to maintain update atomicity. If your system does not
implement a global monitor, this option can cause programs that
perform SWP operations to uncached memory to deadlock.
If unsure, say Y.
config [31mCONFIG_CPU_BIG_ENDIAN[0m
bool "Build big-endian kernel"
depends on [31mCONFIG_ARCH_SUPPORTS_BIG_ENDIAN[0m
help
Say Y if you plan on running a kernel in big-endian mode.
Note that your board must be properly built and your board
port must properly enable any big-endian related features
of your chipset/board/processor.
config [31mCONFIG_CPU_ENDIAN_BE8[0m
bool
depends on [31mCONFIG_CPU_BIG_ENDIAN[0m
default [31mCONFIG_CPU_V6[0m || [31mCONFIG_CPU_V6K[0m || [31mCONFIG_CPU_V7[0m
help
Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
config [31mCONFIG_CPU_ENDIAN_BE32[0m
bool
depends on [31mCONFIG_CPU_BIG_ENDIAN[0m
default ![31mCONFIG_CPU_ENDIAN_BE8[0m
help
Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
config [31mCONFIG_CPU_HIGH_VECTOR[0m
depends on ![31mCONFIG_MMU[0m && [31mCONFIG_CPU_CP15[0m && ![31mCONFIG_CPU_ARM740T[0m
bool "Select the High exception vector"
help
Say Y here to select high exception vector(0xFFFF0000~).
The exception vector can vary depending on the platform
design in nommu mode. If your platform needs to select
high exception vector, say Y.
Otherwise or if you are unsure, say N, and the low exception
vector (0x00000000~) will be used.
config [31mCONFIG_CPU_ICACHE_DISABLE[0m
bool "Disable I-Cache (I-bit)"
depends on ([31mCONFIG_CPU_CP15[0m && !([31mCONFIG_CPU_ARM720T[0m || [31mCONFIG_CPU_ARM740T[0m || [31mCONFIG_CPU_XSCALE[0m || [31mCONFIG_CPU_XSC3[0m)) || [31mCONFIG_CPU_V7M[0m
help
Say Y here to disable the processor instruction cache. Unless
you have a reason not to or are unsure, say N.
config [31mCONFIG_CPU_ICACHE_MISMATCH_WORKAROUND[0m
bool "Workaround for I-Cache line size mismatch between CPU cores"
depends on [31mCONFIG_SMP[0m && [31mCONFIG_CPU_V7[0m
help
Some big.LITTLE systems have I-Cache line size mismatch between
LITTLE and big cores. Say Y here to enable a workaround for
proper I-Cache support on such systems. If unsure, say N.
config [31mCONFIG_CPU_DCACHE_DISABLE[0m
bool "Disable D-Cache (C-bit)"
depends on ([31mCONFIG_CPU_CP15[0m && ![31mCONFIG_SMP[0m) || [31mCONFIG_CPU_V7M[0m
help
Say Y here to disable the processor data cache. Unless
you have a reason not to or are unsure, say N.
config [31mCONFIG_CPU_DCACHE_SIZE[0m
hex
depends on [31mCONFIG_CPU_ARM740T[0m || [31mCONFIG_CPU_ARM946E[0m
default 0x00001000 if [31mCONFIG_CPU_ARM740T[0m
default 0x00002000 # default size for ARM946E-S
help
Some cores are synthesizable to have various sized cache. For
ARM946E-S case, it can vary from 0KB to 1MB.
To support such cache operations, it is efficient to know the size
before compile time.
If your SoC is configured to have a different size, define the value
here with proper conditions.
config [31mCONFIG_CPU_DCACHE_WRITETHROUGH[0m
bool "Force write through D-cache"
depends on ([31mCONFIG_CPU_ARM740T[0m || [31mCONFIG_CPU_ARM920T[0m || [31mCONFIG_CPU_ARM922T[0m || [31mCONFIG_CPU_ARM925T[0m || [31mCONFIG_CPU_ARM926T[0m || [31mCONFIG_CPU_ARM940T[0m || [31mCONFIG_CPU_ARM946E[0m || [31mCONFIG_CPU_ARM1020[0m || [31mCONFIG_CPU_FA526[0m) && ![31mCONFIG_CPU_DCACHE_DISABLE[0m
default y if [31mCONFIG_CPU_ARM925T[0m
help
Say Y here to use the data cache in writethrough mode. Unless you
specifically require this or are unsure, say N.
config [31mCONFIG_CPU_CACHE_ROUND_ROBIN[0m
bool "Round robin I and D cache replacement algorithm"
depends on ([31mCONFIG_CPU_ARM926T[0m || [31mCONFIG_CPU_ARM946E[0m || [31mCONFIG_CPU_ARM1020[0m) && (![31mCONFIG_CPU_ICACHE_DISABLE[0m || ![31mCONFIG_CPU_DCACHE_DISABLE[0m)
help
Say Y here to use the predictable round-robin cache replacement
policy. Unless you specifically require this or are unsure, say N.
config [31mCONFIG_CPU_BPREDICT_DISABLE[0m
bool "Disable branch prediction"
depends on [31mCONFIG_CPU_ARM1020[0m || [31mCONFIG_CPU_V6[0m || [31mCONFIG_CPU_V6K[0m || [31mCONFIG_CPU_MOHAWK[0m || [31mCONFIG_CPU_XSC3[0m || [31mCONFIG_CPU_V7[0m || [31mCONFIG_CPU_FA526[0m || [31mCONFIG_CPU_V7M[0m
help
Say Y here to disable branch prediction. If unsure, say N.
config [31mCONFIG_CPU_SPECTRE[0m
bool
config [31mCONFIG_HARDEN_BRANCH_PREDICTOR[0m
bool "Harden the branch predictor against aliasing attacks" if [31mCONFIG_EXPERT[0m
depends on [31mCONFIG_CPU_SPECTRE[0m
default y
help
Speculation attacks against some high-performance processors rely
on being able to manipulate the branch predictor for a victim
context by executing aliasing branches in the attacker context.
Such attacks can be partially mitigated against by clearing
internal branch predictor state and limiting the prediction
logic in some situations.
This config option will take CPU-specific actions to harden
the branch predictor against aliasing attacks and may rely on
specific instruction sequences or control bits being set by
the system firmware.
If unsure, say Y.
config [31mCONFIG_TLS_REG_EMUL[0m
bool
select [31mCONFIG_NEED_KUSER_HELPERS[0m
help
An [31mCONFIG_SMP[0m system using a pre-ARMv6 processor (there are apparently
a few prototypes like that in existence) and therefore access to
that required register must be emulated.
config [31mCONFIG_NEED_KUSER_HELPERS[0m
bool
config [31mCONFIG_KUSER_HELPERS[0m
bool "Enable kuser helpers in vector page" if ![31mCONFIG_NEED_KUSER_HELPERS[0m
depends on [31mCONFIG_MMU[0m
default y
help
Warning: disabling this option may break user programs.
Provide kuser helpers in the vector page. The kernel provides
helper code to userspace in read only form at a fixed location
in the high vector page to allow userspace to be independent of
the CPU type fitted to the system. This permits binaries to be
run on ARMv4 through to ARMv7 without modification.
See Documentation/arm/kernel_user_helpers.rst for details.
However, the fixed address nature of these helpers can be used
by ROP (return orientated programming) authors when creating
exploits.
If all of the binaries and libraries which run on your platform
are built specifically for your platform, and make no use of
these helpers, then you can turn this option off to hinder
such exploits. However, in that case, if a binary or library
relying on those helpers is run, it will receive a SIGILL signal,
which will terminate the program.
Say N here only if you are absolutely certain that you do not
need these helpers; otherwise, the safe option is to say Y.
config [31mCONFIG_VDSO[0m
bool "Enable VDSO for acceleration of some system calls"
depends on [31mCONFIG_AEABI[0m && [31mCONFIG_MMU[0m && [31mCONFIG_CPU_V7[0m
default y if [31mCONFIG_ARM_ARCH_TIMER[0m
select [31mCONFIG_GENERIC_TIME_VSYSCALL[0m
help
Place in the process address space an ELF shared object
providing fast implementations of gettimeofday and
clock_gettime. Systems that implement the [31mCONFIG_ARM[0m architected
timer will receive maximum benefit.
You must have glibc 2.22 or later for programs to seamlessly
take advantage of this.
config [31mCONFIG_DMA_CACHE_RWFO[0m
bool "Enable read/write for ownership DMA cache maintenance"
depends on [31mCONFIG_CPU_V6K[0m && [31mCONFIG_SMP[0m
default y
help
The Snoop Control Unit on ARM11MPCore does not detect the
cache maintenance operations and the dma_{map,unmap}_area()
functions may leave stale cache entries on other CPUs. By
enabling this option, Read or Write For Ownership in the ARMv6
DMA cache maintenance functions is performed. These LDR/STR
instructions change the cache line state to shared or modified
so that the cache operation has the desired effect.
Note that the workaround is only valid on processors that do
not perform speculative loads into the [31mCONFIG_D[0m-cache. For such
processors, if cache maintenance operations are not broadcast
in hardware, other workarounds are needed (e.g. cache
maintenance broadcasting in software via [31mCONFIG_FIQ[0m).
config [31mCONFIG_OUTER_CACHE[0m
bool
config [31mCONFIG_OUTER_CACHE_SYNC[0m
bool
select [31mCONFIG_ARM_HEAVY_MB[0m
help
The outer cache has a outer_cache_fns.sync function pointer
that can be used to drain the write buffer of the outer cache.
config [31mCONFIG_CACHE_B15_RAC[0m
bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
depends on [31mCONFIG_ARCH_BRCMSTB[0m
default y
help
This option enables the Broadcom Brahma-B15 read-ahead cache
controller. If disabled, the read-ahead cache remains off.
config [31mCONFIG_CACHE_FEROCEON_L2[0m
bool "Enable the Feroceon L2 cache controller"
depends on [31mCONFIG_ARCH_MV78XX0[0m || [31mCONFIG_ARCH_MVEBU[0m
default y
select [31mCONFIG_OUTER_CACHE[0m
help
This option enables the Feroceon L2 cache controller.
config [31mCONFIG_CACHE_FEROCEON_L2_WRITETHROUGH[0m
bool "Force Feroceon L2 cache write through"
depends on [31mCONFIG_CACHE_FEROCEON_L2[0m
help
Say Y here to use the Feroceon L2 cache in writethrough mode.
Unless you specifically require this, say N for writeback mode.
config [31mCONFIG_MIGHT_HAVE_CACHE_L2X0[0m
bool
help
This option should be selected by machines which have a L2x0
or PL310 cache controller, but where its use is optional.
The only effect of this option is to make [31mCONFIG_CACHE_L2X0[0m and
related options available to the user for configuration.
Boards or SoCs which always require the cache controller
support to be present should select [31mCONFIG_CACHE_L2X0[0m directly
instead of this option, thus preventing the user from
inadvertently configuring a broken kernel.
config [31mCONFIG_CACHE_L2X0[0m
bool "Enable the L2x0 outer cache controller" if [31mCONFIG_MIGHT_HAVE_CACHE_L2X0[0m
default [31mCONFIG_MIGHT_HAVE_CACHE_L2X0[0m
select [31mCONFIG_OUTER_CACHE[0m
select [31mCONFIG_OUTER_CACHE_SYNC[0m
help
This option enables the L2x0 PrimeCell.
config [31mCONFIG_CACHE_L2X0_PMU[0m
bool "L2x0 performance monitor support" if [31mCONFIG_CACHE_L2X0[0m
depends on [31mCONFIG_PERF_EVENTS[0m
help
This option enables support for the performance monitoring features
of the L220 and PL310 outer cache controllers.
if [31mCONFIG_CACHE_L2X0[0m
config [31mCONFIG_PL310_ERRATA_588369[0m
bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
help
The PL310 L2 cache controller implements three types of Clean &
Invalidate maintenance operations: by Physical Address
(offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
They are architecturally defined to behave as the execution of a
clean operation followed immediately by an invalidate operation,
both performing to the same memory location. This functionality
is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
as clean lines are not invalidated as a result of these operations.
config [31mCONFIG_PL310_ERRATA_727915[0m
bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
help
PL310 implements the Clean & Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that
PL310 can handle normal accesses while it is in progress. Under very
rare circumstances, due to this erratum, write data can be lost when
PL310 treats a cacheable write transaction during a Clean &
Invalidate by Way operation. Revisions prior to r3p1 are affected by
this errata (fixed in r3p1).
config [31mCONFIG_PL310_ERRATA_753970[0m
bool "PL310 errata: cache sync operation may be faulty"
help
This option enables the workaround for the 753970 PL310 (r3p0) erratum.
Under some condition the effect of cache sync operation on
the store buffer still remains when the operation completes.
This means that the store buffer is always asked to drain and
this prevents it from merging any further writes. The workaround
is to replace the normal offset of cache sync operation (0x730)
by another offset targeting an unmapped PL310 register 0x740.
This has the same effect as the cache sync operation: store buffer
drain and waiting for all buffers empty.
config [31mCONFIG_PL310_ERRATA_769419[0m
bool "PL310 errata: no automatic Store Buffer drain"
help
On revisions of the PL310 prior to r3p2, the Store Buffer does
not automatically drain. This can cause normal, non-cacheable
writes to be retained when the memory system is idle, leading
to suboptimal I/O performance for drivers using coherent DMA.
This option adds a write barrier to the cpu_idle loop so that,
on systems with an outer cache, the store buffer is drained
explicitly.
endif
config [31mCONFIG_CACHE_TAUROS2[0m
bool "Enable the Tauros2 L2 cache controller"
depends on ([31mCONFIG_ARCH_DOVE[0m || [31mCONFIG_ARCH_MMP[0m || [31mCONFIG_CPU_PJ4[0m)
default y
select [31mCONFIG_OUTER_CACHE[0m
help
This option enables the Tauros2 L2 cache controller (as
found on PJ1/PJ4).
config [31mCONFIG_CACHE_UNIPHIER[0m
bool "Enable the UniPhier outer cache controller"
depends on [31mCONFIG_ARCH_UNIPHIER[0m
select [31mCONFIG_ARM_L1_CACHE_SHIFT_7[0m
select [31mCONFIG_OUTER_CACHE[0m
select [31mCONFIG_OUTER_CACHE_SYNC[0m
help
This option enables the UniPhier outer cache (system cache)
controller.
config [31mCONFIG_CACHE_XSC3L2[0m
bool "Enable the L2 cache on XScale3"
depends on [31mCONFIG_CPU_XSC3[0m
default y
select [31mCONFIG_OUTER_CACHE[0m
help
This option enables the L2 cache on XScale3.
config [31mCONFIG_ARM_L1_CACHE_SHIFT_6[0m
bool
default y if [31mCONFIG_CPU_V7[0m
help
Setting [31mCONFIG_ARM[0m L1 cache line size to 64 Bytes.
config [31mCONFIG_ARM_L1_CACHE_SHIFT_7[0m
bool
help
Setting [31mCONFIG_ARM[0m L1 cache line size to 128 Bytes.
config [31mCONFIG_ARM_L1_CACHE_SHIFT[0m
int
default 7 if [31mCONFIG_ARM_L1_CACHE_SHIFT_7[0m
default 6 if [31mCONFIG_ARM_L1_CACHE_SHIFT_6[0m
default 5
config [31mCONFIG_ARM_DMA_MEM_BUFFERABLE[0m
bool "Use non-cacheable memory for DMA" if ([31mCONFIG_CPU_V6[0m || [31mCONFIG_CPU_V6K[0m || [31mCONFIG_CPU_V7M[0m) && ![31mCONFIG_CPU_V7[0m
default y if [31mCONFIG_CPU_V6[0m || [31mCONFIG_CPU_V6K[0m || [31mCONFIG_CPU_V7[0m || [31mCONFIG_CPU_V7M[0m
help
Historically, the kernel has used strongly ordered mappings to
provide DMA coherent memory. With the advent of ARMv7, mapping
memory with differing types results in unpredictable behaviour,
so on these CPUs, this option is forced on.
Multiple mappings with differing attributes is also unpredictable
on ARMv6 CPUs, but since they do not have aggressive speculative
prefetch, no harm appears to occur.
However, drivers may be missing the necessary barriers for ARMv6,
and therefore turning this on may result in unpredictable driver
behaviour. Therefore, we offer this as an option.
On some of the beefier ARMv7-[31mCONFIG_M[0m machines (with DMA and write
buffers) you likely want this enabled, while those that
didn't need it until now also won't need it in the future.
You are recommended say 'Y' here and debug any affected drivers.
config [31mCONFIG_ARM_HEAVY_MB[0m
bool
config [31mCONFIG_ARCH_SUPPORTS_BIG_ENDIAN[0m
bool
help
This option specifies the architecture can support big endian
operation.
config [31mCONFIG_DEBUG_ALIGN_RODATA[0m
bool "Make rodata strictly non-executable"
depends on [31mCONFIG_STRICT_KERNEL_RWX[0m
default y
help
If this is set, rodata will be made explicitly non-executable. This
provides protection on the rare chance that attackers might find and
use ROP gadgets that exist in the rodata section. This adds an
additional section-aligned split of rodata from kernel text so it
can be made explicitly non-executable. This padding may waste memory
space to gain the additional protection.