# SPDX-License-Identifier: GPL-2.0-only
menu "Platform options"
comment "Memory settings"
config [31mCONFIG_NIOS2_MEM_BASE[0m
hex "Memory base address"
default "0x00000000"
help
This is the physical address of the memory that the kernel will run
from. This address is used to link the kernel and setup initial memory
management. You should take the raw memory address without any [31mCONFIG_MMU[0m
or cache bits set.
Please not that this address is used directly so you have to manually
do address translation if it's connected to a bridge.
comment "Device tree"
config [31mCONFIG_NIOS2_DTB_AT_PHYS_ADDR[0m
bool "DTB at physical address"
help
When enabled you can select a physical address to load the dtb from.
Normally this address is passed by a bootloader such as u-boot but
using this you can use a devicetree without a bootloader.
This way you can store a devicetree in NOR flash or an onchip rom.
Please note that this address is used directly so you have to manually
do address translation if it's connected to a bridge. Also take into
account that when using an [31mCONFIG_MMU[0m you'd have to ad 0xC0000000 to your
address
config [31mCONFIG_NIOS2_DTB_PHYS_ADDR[0m
hex "DTB Address"
depends on [31mCONFIG_NIOS2_DTB_AT_PHYS_ADDR[0m
default "0xC0000000"
help
Physical address of a dtb blob.
config [31mCONFIG_NIOS2_DTB_SOURCE_BOOL[0m
bool "Compile and link device tree into kernel image"
help
This allows you to specify a dts (device tree source) file
which will be compiled and linked into the kernel image.
config [31mCONFIG_NIOS2_DTB_SOURCE[0m
string "Device tree source file"
depends on [31mCONFIG_NIOS2_DTB_SOURCE_BOOL[0m
default ""
help
Absolute path to the device tree source (dts) file describing your
system.
comment "Nios II instructions"
config [31mCONFIG_NIOS2_ARCH_REVISION[0m
int "Select Nios II architecture revision"
range 1 2
default 1
help
Select between Nios II R1 and Nios II R2 . The architectures
are binary incompatible. Default is R1 .
config [31mCONFIG_NIOS2_HW_MUL_SUPPORT[0m
bool "Enable MUL instruction"
help
Set to true if you configured the Nios II to include the MUL
instruction. This will enable the -mhw-mul compiler flag.
config [31mCONFIG_NIOS2_HW_MULX_SUPPORT[0m
bool "Enable MULX instruction"
help
Set to true if you configured the Nios II to include the MULX
instruction. Enables the -mhw-mulx compiler flag.
config [31mCONFIG_NIOS2_HW_DIV_SUPPORT[0m
bool "Enable DIV instruction"
help
Set to true if you configured the Nios II to include the DIV
instruction. Enables the -mhw-div compiler flag.
config [31mCONFIG_NIOS2_BMX_SUPPORT[0m
bool "Enable BMX instructions"
depends on [31mCONFIG_NIOS2_ARCH_REVISION[0m = 2
help
Set to true if you configured the Nios II R2 to include
the BMX Bit Manipulation Extension instructions. Enables
the -mbmx compiler flag.
config [31mCONFIG_NIOS2_CDX_SUPPORT[0m
bool "Enable CDX instructions"
depends on [31mCONFIG_NIOS2_ARCH_REVISION[0m = 2
help
Set to true if you configured the Nios II R2 to include
the CDX Bit Manipulation Extension instructions. Enables
the -mcdx compiler flag.
config [31mCONFIG_NIOS2_FPU_SUPPORT[0m
bool "Custom floating point instr support"
help
Enables the -mcustom-fpu-cfg=60-1 compiler flag.
config [31mCONFIG_NIOS2_CI_SWAB_SUPPORT[0m
bool "Byteswap custom instruction"
help
Use the byteswap (endian converter) Nios II custom instruction provided
by Altera and which can be enabled in QSYS builder. This accelerates
endian conversions in the kernel (e.g. ntohs).
config [31mCONFIG_NIOS2_CI_SWAB_NO[0m
int "Byteswap custom instruction number" if [31mCONFIG_NIOS2_CI_SWAB_SUPPORT[0m
default 0
help
Number of the instruction as configured in QSYS Builder.
comment "Cache settings"
config [31mCONFIG_CUSTOM_CACHE_SETTINGS[0m
bool "Custom cache settings"
help
This option allows you to tweak the cache settings used during early
boot (where the information from device tree is not yet available).
There should be no reason to change these values. Linux will work
perfectly fine, even if the Nios II is configured with smaller caches.
Say N here unless you know what you are doing.
config [31mCONFIG_NIOS2_DCACHE_SIZE[0m
hex "D-Cache size" if [31mCONFIG_CUSTOM_CACHE_SETTINGS[0m
range 0x200 0x10000
default "0x800"
help
Maximum possible data cache size.
config [31mCONFIG_NIOS2_DCACHE_LINE_SIZE[0m
hex "D-Cache line size" if [31mCONFIG_CUSTOM_CACHE_SETTINGS[0m
range 0x10 0x20
default "0x20"
help
Minimum possible data cache line size.
config [31mCONFIG_NIOS2_ICACHE_SIZE[0m
hex "I-Cache size" if [31mCONFIG_CUSTOM_CACHE_SETTINGS[0m
range 0x200 0x10000
default "0x1000"
help
Maximum possible instruction cache size.
endmenu