/*
 * P5040 Silicon/SoC Device Tree Source (pre include)
 *
 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * This software is provided by Freescale Semiconductor "as is" and any
 * express or implied warranties, including, but not limited to, the implied
 * warranties of merchantability and fitness for a particular purpose are
 * disclaimed. In no event shall Freescale Semiconductor be liable for any
 * direct, indirect, incidental, special, exemplary, or consequential damages
 * (including, but not limited to, procurement of substitute goods or services;
 * loss of use, data, or profits; or business interruption) however caused and
 * on any theory of liability, whether in contract, strict liability, or tort
 * (including negligence or otherwise) arising in any way out of the use of this
 * software, even if advised of the possibility of such damage.
 */

/dts-v1/;

/include/ "e5500_power_isa.dtsi"

/ {
	compatible = "fsl,P5040";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&mpic>;

	aliases {
		ccsr = &soc;
		dcsr = &dcsr;

		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		serial3 = &serial3;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
		usb0 = &usb0;
		usb1 = &usb1;
		dma0 = &dma0;
		dma1 = &dma1;
		sdhc = &sdhc;
		msi0 = &msi0;
		msi1 = &msi1;
		msi2 = &msi2;

		crypto = &crypto;
		sec_jr0 = &sec_jr0;
		sec_jr1 = &sec_jr1;
		sec_jr2 = &sec_jr2;
		sec_jr3 = &sec_jr3;
		rtic_a = &rtic_a;
		rtic_b = &rtic_b;
		rtic_c = &rtic_c;
		rtic_d = &rtic_d;
		sec_mon = &sec_mon;

		raideng = &raideng;
		raideng_jr0 = &raideng_jr0;
		raideng_jr1 = &raideng_jr1;
		raideng_jr2 = &raideng_jr2;
		raideng_jr3 = &raideng_jr3;

		fman0 = &fman0;
		fman1 = &fman1;
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		ethernet4 = &enet4;
		ethernet5 = &enet5;
		ethernet6 = &enet6;
		ethernet7 = &enet7;
		ethernet8 = &enet8;
		ethernet9 = &enet9;
		ethernet10 = &enet10;
		ethernet11 = &enet11;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: PowerPC,e5500@0 {
			device_type = "cpu";
			reg = <0>;
			clocks = <&clockgen 1 0>;
			next-level-cache = <&L2_0>;
			fsl,portid-mapping = <0x80000000>;
			L2_0: l2-cache {
				next-level-cache = <&cpc>;
			};
		};
		cpu1: PowerPC,e5500@1 {
			device_type = "cpu";
			reg = <1>;
			clocks = <&clockgen 1 1>;
			next-level-cache = <&L2_1>;
			fsl,portid-mapping = <0x40000000>;
			L2_1: l2-cache {
				next-level-cache = <&cpc>;
			};
		};
		cpu2: PowerPC,e5500@2 {
			device_type = "cpu";
			reg = <2>;
			clocks = <&clockgen 1 2>;
			next-level-cache = <&L2_2>;
			fsl,portid-mapping = <0x20000000>;
			L2_2: l2-cache {
				next-level-cache = <&cpc>;
			};
		};
		cpu3: PowerPC,e5500@3 {
			device_type = "cpu";
			reg = <3>;
			clocks = <&clockgen 1 3>;
			next-level-cache = <&L2_3>;
			fsl,portid-mapping = <0x10000000>;
			L2_3: l2-cache {
				next-level-cache = <&cpc>;
			};
		};
	};
};