# SPDX-License-Identifier: GPL-2.0-only
menuconfig [31mCONFIG_CRYPTO_HW[0m
bool "Hardware crypto devices"
default y
---help---
Say Y here to get to see options for hardware crypto devices and
processors. This option alone does not add any kernel code.
If you say N, all options in this submenu will be skipped and disabled.
if [31mCONFIG_CRYPTO_HW[0m
config [31mCONFIG_CRYPTO_DEV_PADLOCK[0m
tristate "Support for VIA PadLock ACE"
depends on [31mCONFIG_X86[0m && ![31mCONFIG_UML[0m
help
Some VIA processors come with an integrated crypto engine
(so called VIA PadLock ACE, Advanced Cryptography Engine)
that provides instructions for very fast cryptographic
operations with supported algorithms.
The instructions are used only when the CPU supports them.
Otherwise software encryption is used.
config [31mCONFIG_CRYPTO_DEV_PADLOCK_AES[0m
tristate "PadLock driver for AES algorithm"
depends on [31mCONFIG_CRYPTO_DEV_PADLOCK[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_LIB_AES[0m
help
Use VIA PadLock for AES algorithm.
Available in VIA C3 and newer CPUs.
If unsure say [31mCONFIG_M[0m. The compiled module will be
called padlock-aes.
config [31mCONFIG_CRYPTO_DEV_PADLOCK_SHA[0m
tristate "PadLock driver for SHA1 and SHA256 algorithms"
depends on [31mCONFIG_CRYPTO_DEV_PADLOCK[0m
select [31mCONFIG_CRYPTO_HASH[0m
select [31mCONFIG_CRYPTO_SHA1[0m
select [31mCONFIG_CRYPTO_SHA256[0m
help
Use VIA PadLock for SHA1/SHA256 algorithms.
Available in VIA C7 and newer processors.
If unsure say [31mCONFIG_M[0m. The compiled module will be
called padlock-sha.
config [31mCONFIG_CRYPTO_DEV_GEODE[0m
tristate "Support for the Geode LX AES engine"
depends on [31mCONFIG_X86_32[0m && [31mCONFIG_PCI[0m
select [31mCONFIG_CRYPTO_ALGAPI[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
help
Say 'Y' here to use the AMD Geode LX processor on-board AES
engine for the CryptoAPI AES algorithm.
To compile this driver as a module, choose [31mCONFIG_M[0m here: the module
will be called geode-aes.
config [31mCONFIG_ZCRYPT[0m
tristate "Support for s390 cryptographic adapters"
depends on [31mCONFIG_S390[0m
select [31mCONFIG_HW_RANDOM[0m
help
Select this option if you want to enable support for
s390 cryptographic adapters like:
+ [31mCONFIG_PCI[0m-X Cryptographic Coprocessor (PCIXCC)
+ Crypto Express 2,3,4 or 5 Coprocessor (CEXxC)
+ Crypto Express 2,3,4 or 5 Accelerator (CEXxA)
+ Crypto Express 4 or 5 EP11 Coprocessor (CEXxP)
config [31mCONFIG_ZCRYPT_MULTIDEVNODES[0m
bool "Support for multiple zcrypt device nodes"
default y
depends on [31mCONFIG_S390[0m
depends on [31mCONFIG_ZCRYPT[0m
help
With this option enabled the zcrypt device driver can
provide multiple devices nodes in /dev. Each device
node can get customized to limit access and narrow
down the use of the available crypto hardware.
config [31mCONFIG_PKEY[0m
tristate "Kernel API for protected key handling"
depends on [31mCONFIG_S390[0m
depends on [31mCONFIG_ZCRYPT[0m
help
With this option enabled the pkey kernel module provides an API
for creation and handling of protected keys. Other parts of the
kernel or userspace applications may use these functions.
Select this option if you want to enable the kernel and userspace
API for proteced key handling.
Please note that creation of protected keys from secure keys
requires to have at least one CEX card in coprocessor mode
available at runtime.
config [31mCONFIG_CRYPTO_PAES_S390[0m
tristate "PAES cipher algorithms"
depends on [31mCONFIG_S390[0m
depends on [31mCONFIG_ZCRYPT[0m
depends on [31mCONFIG_PKEY[0m
select [31mCONFIG_CRYPTO_ALGAPI[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
help
This is the s390 hardware accelerated implementation of the
AES cipher algorithms for use with protected key.
Select this option if you want to use the paes cipher
for example to use protected key encrypted devices.
config [31mCONFIG_CRYPTO_SHA1_S390[0m
tristate "SHA1 digest algorithm"
depends on [31mCONFIG_S390[0m
select [31mCONFIG_CRYPTO_HASH[0m
help
This is the s390 hardware accelerated implementation of the
SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
It is available as of z990.
config [31mCONFIG_CRYPTO_SHA256_S390[0m
tristate "SHA256 digest algorithm"
depends on [31mCONFIG_S390[0m
select [31mCONFIG_CRYPTO_HASH[0m
help
This is the s390 hardware accelerated implementation of the
SHA256 secure hash standard (DFIPS 180-2).
It is available as of z9.
config [31mCONFIG_CRYPTO_SHA512_S390[0m
tristate "SHA384 and SHA512 digest algorithm"
depends on [31mCONFIG_S390[0m
select [31mCONFIG_CRYPTO_HASH[0m
help
This is the s390 hardware accelerated implementation of the
SHA512 secure hash standard.
It is available as of z10.
config [31mCONFIG_CRYPTO_SHA3_256_S390[0m
tristate "SHA3_224 and SHA3_256 digest algorithm"
depends on [31mCONFIG_S390[0m
select [31mCONFIG_CRYPTO_HASH[0m
help
This is the s390 hardware accelerated implementation of the
SHA3_256 secure hash standard.
It is available as of z14.
config [31mCONFIG_CRYPTO_SHA3_512_S390[0m
tristate "SHA3_384 and SHA3_512 digest algorithm"
depends on [31mCONFIG_S390[0m
select [31mCONFIG_CRYPTO_HASH[0m
help
This is the s390 hardware accelerated implementation of the
SHA3_512 secure hash standard.
It is available as of z14.
config [31mCONFIG_CRYPTO_DES_S390[0m
tristate "DES and Triple DES cipher algorithms"
depends on [31mCONFIG_S390[0m
select [31mCONFIG_CRYPTO_ALGAPI[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_LIB_DES[0m
help
This is the s390 hardware accelerated implementation of the
DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
As of z990 the ECB and CBC mode are hardware accelerated.
As of z196 the CTR mode is hardware accelerated.
config [31mCONFIG_CRYPTO_AES_S390[0m
tristate "AES cipher algorithms"
depends on [31mCONFIG_S390[0m
select [31mCONFIG_CRYPTO_ALGAPI[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
help
This is the s390 hardware accelerated implementation of the
AES cipher algorithms (FIPS-197).
As of z9 the ECB and CBC modes are hardware accelerated
for 128 bit keys.
As of z10 the ECB and CBC modes are hardware accelerated
for all AES key sizes.
As of z196 the CTR mode is hardware accelerated for all AES
key sizes and XTS mode is hardware accelerated for 256 and
512 bit keys.
config [31mCONFIG_S390_PRNG[0m
tristate "Pseudo random number generator device driver"
depends on [31mCONFIG_S390[0m
default "m"
help
Select this option if you want to use the s390 pseudo random number
generator. The PRNG is part of the cryptographic processor functions
and uses triple-DES to generate secure random numbers like the
ANSI X9.17 standard. User-space programs access the
pseudo-random-number device through the char device /dev/prandom.
It is available as of z9.
config [31mCONFIG_CRYPTO_GHASH_S390[0m
tristate "GHASH hash function"
depends on [31mCONFIG_S390[0m
select [31mCONFIG_CRYPTO_HASH[0m
help
This is the s390 hardware accelerated implementation of GHASH,
the hash function used in GCM (Galois/Counter mode).
It is available as of z196.
config [31mCONFIG_CRYPTO_CRC32_S390[0m
tristate "CRC-32 algorithms"
depends on [31mCONFIG_S390[0m
select [31mCONFIG_CRYPTO_HASH[0m
select [31mCONFIG_CRC32[0m
help
Select this option if you want to use hardware accelerated
implementations of CRC algorithms. With this option, you
can optimize the computation of CRC-32 (IEEE 802.3 Ethernet)
and CRC-32C (Castagnoli).
It is available with IBM z13 or later.
config [31mCONFIG_CRYPTO_DEV_MARVELL_CESA[0m
tristate "Marvell's Cryptographic Engine driver"
depends on [31mCONFIG_PLAT_ORION[0m || [31mCONFIG_ARCH_MVEBU[0m
select [31mCONFIG_CRYPTO_LIB_AES[0m
select [31mCONFIG_CRYPTO_LIB_DES[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_HASH[0m
select [31mCONFIG_SRAM[0m
help
This driver allows you to utilize the Cryptographic Engines and
Security Accelerator (CESA) which can be found on MVEBU and ORION
platforms.
This driver supports CPU offload through DMA transfers.
config [31mCONFIG_CRYPTO_DEV_NIAGARA2[0m
tristate "Niagara2 Stream Processing Unit driver"
select [31mCONFIG_CRYPTO_LIB_DES[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_HASH[0m
select [31mCONFIG_CRYPTO_MD5[0m
select [31mCONFIG_CRYPTO_SHA1[0m
select [31mCONFIG_CRYPTO_SHA256[0m
depends on [31mCONFIG_SPARC64[0m
help
Each core of a Niagara2 processor contains a Stream
Processing Unit, which itself contains several cryptographic
sub-units. One set provides the Modular Arithmetic Unit,
used for [31mCONFIG_SSL[0m offload. The other set provides the Cipher
Group, which can perform encryption, decryption, hashing,
checksumming, and raw copies.
config [31mCONFIG_CRYPTO_DEV_HIFN_795X[0m
tristate "Driver HIFN 795x crypto accelerator chips"
select [31mCONFIG_CRYPTO_LIB_DES[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_HW_RANDOM[0m if [31mCONFIG_CRYPTO_DEV_HIFN_795X_RNG[0m
depends on [31mCONFIG_PCI[0m
depends on ![31mCONFIG_ARCH_DMA_ADDR_T_64BIT[0m
help
This option allows you to have support for HIFN 795x crypto adapters.
config [31mCONFIG_CRYPTO_DEV_HIFN_795X_RNG[0m
bool "HIFN 795x random number generator"
depends on [31mCONFIG_CRYPTO_DEV_HIFN_795X[0m
help
Select this option if you want to enable the random number generator
on the HIFN 795x crypto adapters.
source "drivers/crypto/caam/Kconfig"
config [31mCONFIG_CRYPTO_DEV_TALITOS[0m
tristate "Talitos Freescale Security Engine (SEC)"
select [31mCONFIG_CRYPTO_AEAD[0m
select [31mCONFIG_CRYPTO_AUTHENC[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_HASH[0m
select [31mCONFIG_HW_RANDOM[0m
depends on [31mCONFIG_FSL_SOC[0m
help
Say 'Y' here to use the Freescale Security Engine (SEC)
to offload cryptographic algorithm computation.
The Freescale SEC is present on PowerQUICC '[31mCONFIG_E[0m' processors, such
as the MPC8349E and MPC8548E.
To compile this driver as a module, choose [31mCONFIG_M[0m here: the module
will be called talitos.
config [31mCONFIG_CRYPTO_DEV_TALITOS1[0m
bool "SEC1 (SEC 1.0 and SEC Lite 1.2)"
depends on [31mCONFIG_CRYPTO_DEV_TALITOS[0m
depends on [31mCONFIG_PPC_8xx[0m || [31mCONFIG_PPC_82xx[0m
default y
help
Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0
found on MPC82xx or the Freescale Security Engine (SEC Lite)
version 1.2 found on MPC8xx
config [31mCONFIG_CRYPTO_DEV_TALITOS2[0m
bool "SEC2+ (SEC version 2.0 or upper)"
depends on [31mCONFIG_CRYPTO_DEV_TALITOS[0m
default y if ![31mCONFIG_PPC_8xx[0m
help
Say 'Y' here to use the Freescale Security Engine (SEC)
version 2 and following as found on MPC83xx, MPC85xx, etc ...
config [31mCONFIG_CRYPTO_DEV_IXP4XX[0m
tristate "Driver for IXP4xx crypto hardware acceleration"
depends on [31mCONFIG_ARCH_IXP4XX[0m && [31mCONFIG_IXP4XX_QMGR[0m && [31mCONFIG_IXP4XX_NPE[0m
select [31mCONFIG_CRYPTO_LIB_DES[0m
select [31mCONFIG_CRYPTO_AEAD[0m
select [31mCONFIG_CRYPTO_AUTHENC[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
help
Driver for the IXP4xx NPE crypto engine.
config [31mCONFIG_CRYPTO_DEV_PPC4XX[0m
tristate "Driver AMCC PPC4xx crypto accelerator"
depends on [31mCONFIG_PPC[0m && [31mCONFIG_4xx[0m
select [31mCONFIG_CRYPTO_HASH[0m
select [31mCONFIG_CRYPTO_AEAD[0m
select [31mCONFIG_CRYPTO_LIB_AES[0m
select [31mCONFIG_CRYPTO_CCM[0m
select [31mCONFIG_CRYPTO_CTR[0m
select [31mCONFIG_CRYPTO_GCM[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
help
This option allows you to have support for AMCC crypto acceleration.
config [31mCONFIG_HW_RANDOM_PPC4XX[0m
bool "PowerPC 4xx generic true random number generator support"
depends on [31mCONFIG_CRYPTO_DEV_PPC4XX[0m && [31mCONFIG_HW_RANDOM[0m
default y
---help---
This option provides the kernel-side support for the TRNG hardware
found in the security function of some PowerPC [31mCONFIG_4xx[0m SoCs.
config [31mCONFIG_CRYPTO_DEV_OMAP[0m
tristate "Support for OMAP crypto HW accelerators"
depends on [31mCONFIG_ARCH_OMAP2PLUS[0m
help
OMAP processors have various crypto HW accelerators. Select this if
you want to use the OMAP modules for any of the crypto algorithms.
if [31mCONFIG_CRYPTO_DEV_OMAP[0m
config [31mCONFIG_CRYPTO_DEV_OMAP_SHAM[0m
tristate "Support for OMAP MD5/SHA1/SHA2 hw accelerator"
depends on [31mCONFIG_ARCH_OMAP2PLUS[0m
select [31mCONFIG_CRYPTO_SHA1[0m
select [31mCONFIG_CRYPTO_MD5[0m
select [31mCONFIG_CRYPTO_SHA256[0m
select [31mCONFIG_CRYPTO_SHA512[0m
select [31mCONFIG_CRYPTO_HMAC[0m
help
OMAP processors have MD5/SHA1/SHA2 hw accelerator. Select this if you
want to use the OMAP module for MD5/SHA1/SHA2 algorithms.
config [31mCONFIG_CRYPTO_DEV_OMAP_AES[0m
tristate "Support for OMAP AES hw engine"
depends on [31mCONFIG_ARCH_OMAP2[0m || [31mCONFIG_ARCH_OMAP3[0m || [31mCONFIG_ARCH_OMAP2PLUS[0m
select [31mCONFIG_CRYPTO_AES[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_ENGINE[0m
select [31mCONFIG_CRYPTO_CBC[0m
select [31mCONFIG_CRYPTO_ECB[0m
select [31mCONFIG_CRYPTO_CTR[0m
select [31mCONFIG_CRYPTO_AEAD[0m
help
OMAP processors have AES module accelerator. Select this if you
want to use the OMAP module for AES algorithms.
config [31mCONFIG_CRYPTO_DEV_OMAP_DES[0m
tristate "Support for OMAP DES/3DES hw engine"
depends on [31mCONFIG_ARCH_OMAP2PLUS[0m
select [31mCONFIG_CRYPTO_LIB_DES[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_ENGINE[0m
help
OMAP processors have DES/3DES module accelerator. Select this if you
want to use the OMAP module for DES and 3DES algorithms. Currently
the ECB and CBC modes of operation are supported by the driver. Also
accesses made on unaligned boundaries are supported.
endif # [31mCONFIG_CRYPTO_DEV_OMAP[0m
config [31mCONFIG_CRYPTO_DEV_PICOXCELL[0m
tristate "Support for picoXcell IPSEC and Layer2 crypto engines"
depends on ([31mCONFIG_ARCH_PICOXCELL[0m || [31mCONFIG_COMPILE_TEST[0m) && [31mCONFIG_HAVE_CLK[0m
select [31mCONFIG_CRYPTO_AEAD[0m
select [31mCONFIG_CRYPTO_AES[0m
select [31mCONFIG_CRYPTO_AUTHENC[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_LIB_DES[0m
select [31mCONFIG_CRYPTO_CBC[0m
select [31mCONFIG_CRYPTO_ECB[0m
select [31mCONFIG_CRYPTO_SEQIV[0m
help
This option enables support for the hardware offload engines in the
Picochip picoXcell SoC devices. Select this for IPSEC ESP offload
and for 3gpp Layer 2 ciphering support.
Saying m here will build a module named picoxcell_crypto.
config [31mCONFIG_CRYPTO_DEV_SAHARA[0m
tristate "Support for SAHARA crypto accelerator"
depends on [31mCONFIG_ARCH_MXC[0m && [31mCONFIG_OF[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_AES[0m
select [31mCONFIG_CRYPTO_ECB[0m
help
This option enables support for the SAHARA HW crypto accelerator
found in some Freescale i.MX chips.
config [31mCONFIG_CRYPTO_DEV_EXYNOS_RNG[0m
tristate "EXYNOS HW pseudo random number generator support"
depends on [31mCONFIG_ARCH_EXYNOS[0m || [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_CRYPTO_RNG[0m
---help---
This driver provides kernel-side support through the
cryptographic API for the pseudo random number generator hardware
found on Exynos SoCs.
To compile this driver as a module, choose [31mCONFIG_M[0m here: the
module will be called exynos-rng.
If unsure, say Y.
config [31mCONFIG_CRYPTO_DEV_S5P[0m
tristate "Support for Samsung S5PV210/Exynos crypto accelerator"
depends on [31mCONFIG_ARCH_S5PV210[0m || [31mCONFIG_ARCH_EXYNOS[0m || [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_CRYPTO_AES[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
help
This option allows you to have support for S5P crypto acceleration.
Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES
algorithms execution.
config [31mCONFIG_CRYPTO_DEV_EXYNOS_HASH[0m
bool "Support for Samsung Exynos HASH accelerator"
depends on [31mCONFIG_CRYPTO_DEV_S5P[0m
depends on ![31mCONFIG_CRYPTO_DEV_EXYNOS_RNG[0m && [31mCONFIG_CRYPTO_DEV_EXYNOS_RNG[0m!=m
select [31mCONFIG_CRYPTO_SHA1[0m
select [31mCONFIG_CRYPTO_MD5[0m
select [31mCONFIG_CRYPTO_SHA256[0m
help
Select this to offload Exynos from HASH MD5/SHA1/SHA256.
This will select software SHA1, MD5 and SHA256 as they are
needed for small and zero-size messages.
HASH algorithms will be disabled if EXYNOS_RNG
is enabled due to hw conflict.
config [31mCONFIG_CRYPTO_DEV_NX[0m
bool "Support for IBM PowerPC Nest (NX) cryptographic acceleration"
depends on [31mCONFIG_PPC64[0m
help
This enables support for the NX hardware cryptographic accelerator
coprocessor that is in IBM PowerPC P7+ or later processors. This
does not actually enable any drivers, it only allows you to select
which acceleration type (encryption and/or compression) to enable.
if [31mCONFIG_CRYPTO_DEV_NX[0m
source "drivers/crypto/nx/Kconfig"
endif
config [31mCONFIG_CRYPTO_DEV_UX500[0m
tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration"
depends on [31mCONFIG_ARCH_U8500[0m
help
Driver for ST-Ericsson UX500 crypto engine.
if [31mCONFIG_CRYPTO_DEV_UX500[0m
source "drivers/crypto/ux500/Kconfig"
endif # if [31mCONFIG_CRYPTO_DEV_UX500[0m
config [31mCONFIG_CRYPTO_DEV_ATMEL_AUTHENC[0m
tristate "Support for Atmel IPSEC/SSL hw accelerator"
depends on [31mCONFIG_ARCH_AT91[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CRYPTO_AUTHENC[0m
select [31mCONFIG_CRYPTO_DEV_ATMEL_AES[0m
select [31mCONFIG_CRYPTO_DEV_ATMEL_SHA[0m
help
Some Atmel processors can combine the AES and SHA hw accelerators
to enhance support of IPSEC/[31mCONFIG_SSL[0m.
Select this if you want to use the Atmel modules for
authenc(hmac(shaX),Y(cbc)) algorithms.
config [31mCONFIG_CRYPTO_DEV_ATMEL_AES[0m
tristate "Support for Atmel AES hw accelerator"
depends on [31mCONFIG_ARCH_AT91[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CRYPTO_AES[0m
select [31mCONFIG_CRYPTO_AEAD[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
help
Some Atmel processors have AES hw accelerator.
Select this if you want to use the Atmel module for
AES algorithms.
To compile this driver as a module, choose [31mCONFIG_M[0m here: the module
will be called atmel-aes.
config [31mCONFIG_CRYPTO_DEV_ATMEL_TDES[0m
tristate "Support for Atmel DES/TDES hw accelerator"
depends on [31mCONFIG_ARCH_AT91[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CRYPTO_LIB_DES[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
help
Some Atmel processors have DES/TDES hw accelerator.
Select this if you want to use the Atmel module for
DES/TDES algorithms.
To compile this driver as a module, choose [31mCONFIG_M[0m here: the module
will be called atmel-tdes.
config [31mCONFIG_CRYPTO_DEV_ATMEL_SHA[0m
tristate "Support for Atmel SHA hw accelerator"
depends on [31mCONFIG_ARCH_AT91[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CRYPTO_HASH[0m
help
Some Atmel processors have SHA1/SHA224/SHA256/SHA384/SHA512
hw accelerator.
Select this if you want to use the Atmel module for
SHA1/SHA224/SHA256/SHA384/SHA512 algorithms.
To compile this driver as a module, choose [31mCONFIG_M[0m here: the module
will be called atmel-sha.
config [31mCONFIG_CRYPTO_DEV_ATMEL_I2C[0m
tristate
config [31mCONFIG_CRYPTO_DEV_ATMEL_ECC[0m
tristate "Support for Microchip / Atmel ECC hw accelerator"
depends on [31mCONFIG_I2C[0m
select [31mCONFIG_CRYPTO_DEV_ATMEL_I2C[0m
select [31mCONFIG_CRYPTO_ECDH[0m
select [31mCONFIG_CRC16[0m
help
Microhip / Atmel ECC hw accelerator.
Select this if you want to use the Microchip / Atmel module for
ECDH algorithm.
To compile this driver as a module, choose [31mCONFIG_M[0m here: the module
will be called atmel-ecc.
config [31mCONFIG_CRYPTO_DEV_ATMEL_SHA204A[0m
tristate "Support for Microchip / Atmel SHA accelerator and RNG"
depends on [31mCONFIG_I2C[0m
select [31mCONFIG_CRYPTO_DEV_ATMEL_I2C[0m
select [31mCONFIG_HW_RANDOM[0m
select [31mCONFIG_CRC16[0m
help
Microhip / Atmel SHA accelerator and RNG.
Select this if you want to use the Microchip / Atmel SHA204A
module as a random number generator. (Other functions of the
chip are currently not exposed by this driver)
To compile this driver as a module, choose [31mCONFIG_M[0m here: the module
will be called atmel-sha204a.
config [31mCONFIG_CRYPTO_DEV_CCP[0m
bool "Support for AMD Secure Processor"
depends on (([31mCONFIG_X86[0m && [31mCONFIG_PCI[0m) || ([31mCONFIG_ARM64[0m && ([31mCONFIG_OF_ADDRESS[0m || [31mCONFIG_ACPI[0m))) && [31mCONFIG_HAS_IOMEM[0m
help
The AMD Secure Processor provides support for the Cryptographic Coprocessor
(CCP) and the Platform Security Processor (PSP) devices.
if [31mCONFIG_CRYPTO_DEV_CCP[0m
source "drivers/crypto/ccp/Kconfig"
endif
config [31mCONFIG_CRYPTO_DEV_MXS_DCP[0m
tristate "Support for Freescale MXS DCP"
depends on ([31mCONFIG_ARCH_MXS[0m || [31mCONFIG_ARCH_MXC[0m)
select [31mCONFIG_STMP_DEVICE[0m
select [31mCONFIG_CRYPTO_CBC[0m
select [31mCONFIG_CRYPTO_ECB[0m
select [31mCONFIG_CRYPTO_AES[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_HASH[0m
help
The Freescale i.MX23/i.MX28 has SHA1/SHA256 and AES128 CBC/ECB
co-processor on the die.
To compile this driver as a module, choose [31mCONFIG_M[0m here: the module
will be called mxs-dcp.
source "drivers/crypto/qat/Kconfig"
source "drivers/crypto/cavium/cpt/Kconfig"
source "drivers/crypto/cavium/nitrox/Kconfig"
config [31mCONFIG_CRYPTO_DEV_CAVIUM_ZIP[0m
tristate "Cavium ZIP driver"
depends on [31mCONFIG_PCI[0m && [31mCONFIG_64BIT[0m && ([31mCONFIG_ARM64[0m || [31mCONFIG_COMPILE_TEST[0m)
---help---
Select this option if you want to enable compression/decompression
acceleration on Cavium's [31mCONFIG_ARM[0m based SoCs
config [31mCONFIG_CRYPTO_DEV_QCE[0m
tristate "Qualcomm crypto engine accelerator"
depends on [31mCONFIG_ARCH_QCOM[0m || [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_CRYPTO_AES[0m
select [31mCONFIG_CRYPTO_LIB_DES[0m
select [31mCONFIG_CRYPTO_ECB[0m
select [31mCONFIG_CRYPTO_CBC[0m
select [31mCONFIG_CRYPTO_XTS[0m
select [31mCONFIG_CRYPTO_CTR[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
help
This driver supports Qualcomm crypto engine accelerator
hardware. To compile this driver as a module, choose [31mCONFIG_M[0m here. The
module will be called qcrypto.
config [31mCONFIG_CRYPTO_DEV_QCOM_RNG[0m
tristate "Qualcomm Random Number Generator Driver"
depends on [31mCONFIG_ARCH_QCOM[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CRYPTO_RNG[0m
help
This driver provides support for the Random Number
Generator hardware found on Qualcomm SoCs.
To compile this driver as a module, choose [31mCONFIG_M[0m here. The
module will be called qcom-rng. If unsure, say N.
config [31mCONFIG_CRYPTO_DEV_VMX[0m
bool "Support for VMX cryptographic acceleration instructions"
depends on [31mCONFIG_PPC64[0m && [31mCONFIG_VSX[0m
help
Support for VMX cryptographic acceleration instructions.
source "drivers/crypto/vmx/Kconfig"
config [31mCONFIG_CRYPTO_DEV_IMGTEC_HASH[0m
tristate "Imagination Technologies hardware hash accelerator"
depends on [31mCONFIG_MIPS[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CRYPTO_MD5[0m
select [31mCONFIG_CRYPTO_SHA1[0m
select [31mCONFIG_CRYPTO_SHA256[0m
select [31mCONFIG_CRYPTO_HASH[0m
help
This driver interfaces with the Imagination Technologies
hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256
hashing algorithms.
config [31mCONFIG_CRYPTO_DEV_SUN4I_SS[0m
tristate "Support for Allwinner Security System cryptographic accelerator"
depends on [31mCONFIG_ARCH_SUNXI[0m && ![31mCONFIG_64BIT[0m
select [31mCONFIG_CRYPTO_MD5[0m
select [31mCONFIG_CRYPTO_SHA1[0m
select [31mCONFIG_CRYPTO_AES[0m
select [31mCONFIG_CRYPTO_LIB_DES[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
help
Some Allwinner SoC have a crypto accelerator named
Security System. Select this if you want to use it.
The Security System handle AES/DES/3DES ciphers in CBC mode
and SHA1 and MD5 hash algorithms.
To compile this driver as a module, choose [31mCONFIG_M[0m here: the module
will be called sun4i-ss.
config [31mCONFIG_CRYPTO_DEV_SUN4I_SS_PRNG[0m
bool "Support for Allwinner Security System PRNG"
depends on [31mCONFIG_CRYPTO_DEV_SUN4I_SS[0m
select [31mCONFIG_CRYPTO_RNG[0m
help
Select this option if you want to provide kernel-side support for
the Pseudo-Random Number Generator found in the Security System.
config [31mCONFIG_CRYPTO_DEV_ROCKCHIP[0m
tristate "Rockchip's Cryptographic Engine driver"
depends on [31mCONFIG_OF[0m && [31mCONFIG_ARCH_ROCKCHIP[0m
select [31mCONFIG_CRYPTO_AES[0m
select [31mCONFIG_CRYPTO_LIB_DES[0m
select [31mCONFIG_CRYPTO_MD5[0m
select [31mCONFIG_CRYPTO_SHA1[0m
select [31mCONFIG_CRYPTO_SHA256[0m
select [31mCONFIG_CRYPTO_HASH[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
help
This driver interfaces with the hardware crypto accelerator.
Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
config [31mCONFIG_CRYPTO_DEV_MEDIATEK[0m
tristate "MediaTek's EIP97 Cryptographic Engine driver"
depends on ([31mCONFIG_ARM[0m && [31mCONFIG_ARCH_MEDIATEK[0m) || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CRYPTO_AES[0m
select [31mCONFIG_CRYPTO_AEAD[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_CTR[0m
select [31mCONFIG_CRYPTO_SHA1[0m
select [31mCONFIG_CRYPTO_SHA256[0m
select [31mCONFIG_CRYPTO_SHA512[0m
select [31mCONFIG_CRYPTO_HMAC[0m
help
This driver allows you to utilize the hardware crypto accelerator
EIP97 which can be found on the MT7623 MT2701, MT8521p, etc ....
Select this if you want to use it for AES/SHA1/SHA2 algorithms.
source "drivers/crypto/chelsio/Kconfig"
source "drivers/crypto/virtio/Kconfig"
config [31mCONFIG_CRYPTO_DEV_BCM_SPU[0m
tristate "Broadcom symmetric crypto/hash acceleration support"
depends on [31mCONFIG_ARCH_BCM_IPROC[0m
depends on [31mCONFIG_MAILBOX[0m
default m
select [31mCONFIG_CRYPTO_AUTHENC[0m
select [31mCONFIG_CRYPTO_LIB_DES[0m
select [31mCONFIG_CRYPTO_MD5[0m
select [31mCONFIG_CRYPTO_SHA1[0m
select [31mCONFIG_CRYPTO_SHA256[0m
select [31mCONFIG_CRYPTO_SHA512[0m
help
This driver provides support for Broadcom crypto acceleration using the
Secure Processing Unit (SPU). The SPU driver registers ablkcipher,
ahash, and aead algorithms with the kernel cryptographic API.
source "drivers/crypto/stm32/Kconfig"
config [31mCONFIG_CRYPTO_DEV_SAFEXCEL[0m
tristate "Inside Secure's SafeXcel cryptographic engine driver"
depends on [31mCONFIG_OF[0m || [31mCONFIG_PCI[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_CRYPTO_LIB_AES[0m
select [31mCONFIG_CRYPTO_AUTHENC[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_LIB_DES[0m
select [31mCONFIG_CRYPTO_HASH[0m
select [31mCONFIG_CRYPTO_HMAC[0m
select [31mCONFIG_CRYPTO_MD5[0m
select [31mCONFIG_CRYPTO_SHA1[0m
select [31mCONFIG_CRYPTO_SHA256[0m
select [31mCONFIG_CRYPTO_SHA512[0m
help
This driver interfaces with the SafeXcel EIP-97 and EIP-197 cryptographic
engines designed by Inside Secure. It currently accelerates DES, 3DES and
AES block ciphers in ECB and CBC mode, as well as SHA1, SHA224, SHA256,
SHA384 and SHA512 hash algorithms for both basic hash and HMAC.
Additionally, it accelerates combined AES-CBC/HMAC-SHA AEAD operations.
config [31mCONFIG_CRYPTO_DEV_ARTPEC6[0m
tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
depends on [31mCONFIG_ARM[0m && ([31mCONFIG_ARCH_ARTPEC[0m || [31mCONFIG_COMPILE_TEST[0m)
depends on [31mCONFIG_OF[0m
select [31mCONFIG_CRYPTO_AEAD[0m
select [31mCONFIG_CRYPTO_AES[0m
select [31mCONFIG_CRYPTO_ALGAPI[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_CTR[0m
select [31mCONFIG_CRYPTO_HASH[0m
select [31mCONFIG_CRYPTO_SHA1[0m
select [31mCONFIG_CRYPTO_SHA256[0m
select [31mCONFIG_CRYPTO_SHA512[0m
help
Enables the driver for the on-chip crypto accelerator
of Axis ARTPEC SoCs.
To compile this driver as a module, choose [31mCONFIG_M[0m here.
config [31mCONFIG_CRYPTO_DEV_CCREE[0m
tristate "Support for ARM TrustZone CryptoCell family of security processors"
depends on [31mCONFIG_CRYPTO[0m && [31mCONFIG_CRYPTO_HW[0m && [31mCONFIG_OF[0m && [31mCONFIG_HAS_DMA[0m
default n
select [31mCONFIG_CRYPTO_HASH[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_LIB_DES[0m
select [31mCONFIG_CRYPTO_AEAD[0m
select [31mCONFIG_CRYPTO_AUTHENC[0m
select [31mCONFIG_CRYPTO_SHA1[0m
select [31mCONFIG_CRYPTO_MD5[0m
select [31mCONFIG_CRYPTO_SHA256[0m
select [31mCONFIG_CRYPTO_SHA512[0m
select [31mCONFIG_CRYPTO_HMAC[0m
select [31mCONFIG_CRYPTO_AES[0m
select [31mCONFIG_CRYPTO_CBC[0m
select [31mCONFIG_CRYPTO_ECB[0m
select [31mCONFIG_CRYPTO_CTR[0m
select [31mCONFIG_CRYPTO_XTS[0m
select [31mCONFIG_CRYPTO_SM4[0m
select [31mCONFIG_CRYPTO_SM3[0m
help
Say 'Y' to enable a driver for the REE interface of the Arm
TrustZone CryptoCell family of processors. Currently the
CryptoCell 713, 703, 712, 710 and 630 are supported.
Choose this if you wish to use hardware acceleration of
cryptographic operations on the system REE.
If unsure say Y.
source "drivers/crypto/hisilicon/Kconfig"
endif # [31mCONFIG_CRYPTO_HW[0m