# SPDX-License-Identifier: GPL-2.0-only
menuconfig [31mCONFIG_MAILBOX[0m
bool "Mailbox Hardware Support"
help
Mailbox is a framework to control hardware communication between
on-chip processors through queued messages and interrupt driven
signals. Say Y if your platform supports hardware mailboxes.
if [31mCONFIG_MAILBOX[0m
config [31mCONFIG_ARM_MHU[0m
tristate "ARM MHU Mailbox"
depends on [31mCONFIG_ARM_AMBA[0m
help
Say Y here if you want to build the [31mCONFIG_ARM[0m MHU controller driver.
The controller has 3 mailbox channels, the last of which can be
used in Secure mode only.
config [31mCONFIG_IMX_MBOX[0m
tristate "i.MX Mailbox"
depends on [31mCONFIG_ARCH_MXC[0m || [31mCONFIG_COMPILE_TEST[0m
help
Mailbox implementation for i.MX Messaging Unit (MU).
config [31mCONFIG_PLATFORM_MHU[0m
tristate "Platform MHU Mailbox"
depends on [31mCONFIG_OF[0m
depends on [31mCONFIG_HAS_IOMEM[0m
help
Say Y here if you want to build a platform specific variant MHU
controller driver.
The controller has a maximum of 3 mailbox channels, the last of
which can be used in Secure mode only.
config [31mCONFIG_PL320_MBOX[0m
bool "ARM PL320 Mailbox"
depends on [31mCONFIG_ARM_AMBA[0m
help
An implementation of the [31mCONFIG_ARM[0m PL320 Interprocessor Communication
Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
send short messages between Highbank's A9 cores and the EnergyCore
Management Engine, primarily for cpufreq. Say Y here if you want
to use the PL320 IPCM support.
config [31mCONFIG_ARMADA_37XX_RWTM_MBOX[0m
tristate "Armada 37xx rWTM BIU Mailbox"
depends on [31mCONFIG_ARCH_MVEBU[0m || [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_OF[0m
help
Mailbox implementation for communication with the the firmware
running on the Cortex-M3 rWTM secure processor of the Armada 37xx
SOC. Say Y here if you are building for such a device (for example
the Turris Mox router).
config [31mCONFIG_OMAP2PLUS_MBOX[0m
tristate "OMAP2+ Mailbox framework support"
depends on [31mCONFIG_ARCH_OMAP2PLUS[0m || [31mCONFIG_ARCH_K3[0m
help
Mailbox implementation for OMAP family chips with hardware for
interprocessor communication involving DSP, IVA1.0 and IVA2 in
OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
want to use OMAP2+ Mailbox framework support.
config [31mCONFIG_OMAP_MBOX_KFIFO_SIZE[0m
int "Mailbox kfifo default buffer size (bytes)"
depends on [31mCONFIG_OMAP2PLUS_MBOX[0m
default 256
help
Specify the default size of mailbox's kfifo buffers (bytes).
This can also be changed at runtime (via the mbox_kfifo_size
module parameter).
config [31mCONFIG_ROCKCHIP_MBOX[0m
bool "Rockchip Soc Intergrated Mailbox Support"
depends on [31mCONFIG_ARCH_ROCKCHIP[0m || [31mCONFIG_COMPILE_TEST[0m
help
This driver provides support for inter-processor communication
between CPU cores and MCU processor on Some Rockchip SOCs.
Please check it that the Soc you use have Mailbox hardware.
Say Y here if you want to use the Rockchip Mailbox support.
config [31mCONFIG_PCC[0m
bool "Platform Communication Channel Driver"
depends on [31mCONFIG_ACPI[0m
default n
help
[31mCONFIG_ACPI[0m 5.0+ spec defines a generic mode of communication
between the OS and a platform such as the BMC. This medium
([31mCONFIG_PCC[0m) is typically used by CPPC ([31mCONFIG_ACPI[0m CPU Performance management),
[31mCONFIG_RAS[0m ([31mCONFIG_ACPI[0m reliability protocol) and MPST ([31mCONFIG_ACPI[0m Memory power
states). Select this driver if your platform implements the
[31mCONFIG_PCC[0m clients mentioned above.
config [31mCONFIG_ALTERA_MBOX[0m
tristate "Altera Mailbox"
depends on [31mCONFIG_HAS_IOMEM[0m
help
An implementation of the Altera Mailbox soft core. It is used
to send message between processors. Say Y here if you want to use the
Altera mailbox support.
config [31mCONFIG_BCM2835_MBOX[0m
tristate "BCM2835 Mailbox"
depends on [31mCONFIG_ARCH_BCM2835[0m
help
An implementation of the BCM2385 Mailbox. It is used to invoke
the services of the Videocore. Say Y here if you want to use the
BCM2835 Mailbox.
config [31mCONFIG_STI_MBOX[0m
tristate "STI Mailbox framework support"
depends on [31mCONFIG_ARCH_STI[0m && [31mCONFIG_OF[0m
help
Mailbox implementation for STMicroelectonics family chips with
hardware for interprocessor communication.
config [31mCONFIG_TI_MESSAGE_MANAGER[0m
tristate "Texas Instruments Message Manager Driver"
depends on [31mCONFIG_ARCH_KEYSTONE[0m || [31mCONFIG_ARCH_K3[0m
help
An implementation of Message Manager slave driver for Keystone
and K3 architecture SoCs from Texas Instruments. Message Manager
is a communication entity found on few of Texas Instrument's keystone
and K3 architecture SoCs. These may be used for communication between
multiple processors within the SoC. Select this driver if your
platform has support for the hardware block.
config [31mCONFIG_HI3660_MBOX[0m
tristate "Hi3660 Mailbox" if [31mCONFIG_EXPERT[0m
depends on ([31mCONFIG_ARCH_HISI[0m || [31mCONFIG_COMPILE_TEST[0m)
depends on [31mCONFIG_OF[0m
default [31mCONFIG_ARCH_HISI[0m
help
An implementation of the hi3660 mailbox. It is used to send message
between application processors and other processors/MCU/DSP. Select
Y here if you want to use Hi3660 mailbox controller.
config [31mCONFIG_HI6220_MBOX[0m
tristate "Hi6220 Mailbox" if [31mCONFIG_EXPERT[0m
depends on ([31mCONFIG_ARCH_HISI[0m || [31mCONFIG_COMPILE_TEST[0m)
depends on [31mCONFIG_OF[0m
default [31mCONFIG_ARCH_HISI[0m
help
An implementation of the hi6220 mailbox. It is used to send message
between application processors and MCU. Say Y here if you want to
build Hi6220 mailbox controller driver.
config [31mCONFIG_MAILBOX_TEST[0m
tristate "Mailbox Test Client"
depends on [31mCONFIG_OF[0m
depends on [31mCONFIG_HAS_IOMEM[0m
help
Test client to help with testing new Controller driver
implementations.
config [31mCONFIG_QCOM_APCS_IPC[0m
tristate "Qualcomm APCS IPC driver"
depends on [31mCONFIG_ARCH_QCOM[0m || [31mCONFIG_COMPILE_TEST[0m
help
Say y here to enable support for the APCS IPC mailbox driver,
providing an interface for invoking the inter-process communication
signals from the application processor to other masters.
config [31mCONFIG_TEGRA_HSP_MBOX[0m
bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
depends on [31mCONFIG_ARCH_TEGRA[0m
help
The Tegra HSP driver is used for the interprocessor communication
between different remote processors and host processors on Tegra186
and later SoCs. Say Y here if you want to have this support.
If unsure say N.
config [31mCONFIG_XGENE_SLIMPRO_MBOX[0m
tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
depends on [31mCONFIG_ARCH_XGENE[0m
help
An implementation of the [31mCONFIG_APM[0m X-Gene Interprocessor Communication
Mailbox (IPCM) between the [31mCONFIG_ARM[0m 64-bit cores and SLIMpro controller.
It is used to send short messages between [31mCONFIG_ARM64[0m-bit cores and
the SLIMpro Management Engine, primarily for [31mCONFIG_PM[0m. Say Y here if you
want to use the [31mCONFIG_APM[0m X-Gene SLIMpro IPCM support.
config [31mCONFIG_BCM_PDC_MBOX[0m
tristate "Broadcom FlexSparx DMA Mailbox"
depends on [31mCONFIG_ARCH_BCM_IPROC[0m || [31mCONFIG_COMPILE_TEST[0m
help
Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
which provides access to various offload engines on Broadcom
SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
config [31mCONFIG_BCM_FLEXRM_MBOX[0m
tristate "Broadcom FlexRM Mailbox"
depends on [31mCONFIG_ARM64[0m
depends on [31mCONFIG_ARCH_BCM_IPROC[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_GENERIC_MSI_IRQ_DOMAIN[0m
default m if [31mCONFIG_ARCH_BCM_IPROC[0m
help
Mailbox implementation of the Broadcom FlexRM ring manager,
which provides access to various offload engines on Broadcom
SoCs. Say Y here if you want to use the Broadcom FlexRM.
config [31mCONFIG_STM32_IPCC[0m
tristate "STM32 IPCC Mailbox"
depends on [31mCONFIG_MACH_STM32MP157[0m
help
Mailbox implementation for STMicroelectonics STM32 family chips
with hardware for Inter-Processor Communication Controller (IPCC)
between processors. Say Y here if you want to have this support.
config [31mCONFIG_MTK_CMDQ_MBOX[0m
tristate "MediaTek CMDQ Mailbox Support"
depends on [31mCONFIG_ARCH_MEDIATEK[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_MTK_INFRACFG[0m
help
Say yes here to add support for the MediaTek Command Queue (CMDQ)
mailbox driver. The CMDQ is used to help read/write registers with
critical time limitation, such as updating display configuration
during the vblank.
config [31mCONFIG_ZYNQMP_IPI_MBOX[0m
bool "Xilinx ZynqMP IPI Mailbox"
depends on [31mCONFIG_ARCH_ZYNQMP[0m && [31mCONFIG_OF[0m
help
Say yes here to add support for Xilinx IPI mailbox driver.
This mailbox driver is used to send notification or short message
between processors with Xilinx ZynqMP IPI. It will place the
message to the IPI buffer and will access the IPI control
registers to kick the other processor or enquire status.
endif