# SPDX-License-Identifier: GPL-2.0
menuconfig [31mCONFIG_ARM_CRYPTO[0m
bool "ARM Accelerated Cryptographic Algorithms"
depends on [31mCONFIG_ARM[0m
help
Say Y here to choose from a selection of cryptographic algorithms
implemented using [31mCONFIG_ARM[0m specific CPU features or instructions.
if [31mCONFIG_ARM_CRYPTO[0m
config [31mCONFIG_CRYPTO_SHA1_ARM[0m
tristate "SHA1 digest algorithm (ARM-asm)"
select [31mCONFIG_CRYPTO_SHA1[0m
select [31mCONFIG_CRYPTO_HASH[0m
help
SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
using optimized [31mCONFIG_ARM[0m assembler.
config [31mCONFIG_CRYPTO_SHA1_ARM_NEON[0m
tristate "SHA1 digest algorithm (ARM NEON)"
depends on [31mCONFIG_KERNEL_MODE_NEON[0m
select [31mCONFIG_CRYPTO_SHA1_ARM[0m
select [31mCONFIG_CRYPTO_SHA1[0m
select [31mCONFIG_CRYPTO_HASH[0m
help
SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
using optimized [31mCONFIG_ARM[0m [31mCONFIG_NEON[0m assembly, when [31mCONFIG_NEON[0m instructions are
available.
config [31mCONFIG_CRYPTO_SHA1_ARM_CE[0m
tristate "SHA1 digest algorithm (ARM v8 Crypto Extensions)"
depends on [31mCONFIG_KERNEL_MODE_NEON[0m
select [31mCONFIG_CRYPTO_SHA1_ARM[0m
select [31mCONFIG_CRYPTO_HASH[0m
help
SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
using special ARMv8 Crypto Extensions.
config [31mCONFIG_CRYPTO_SHA2_ARM_CE[0m
tristate "SHA-224/256 digest algorithm (ARM v8 Crypto Extensions)"
depends on [31mCONFIG_KERNEL_MODE_NEON[0m
select [31mCONFIG_CRYPTO_SHA256_ARM[0m
select [31mCONFIG_CRYPTO_HASH[0m
help
SHA-256 secure hash standard (DFIPS 180-2) implemented
using special ARMv8 Crypto Extensions.
config [31mCONFIG_CRYPTO_SHA256_ARM[0m
tristate "SHA-224/256 digest algorithm (ARM-asm and NEON)"
select [31mCONFIG_CRYPTO_HASH[0m
depends on ![31mCONFIG_CPU_V7M[0m
help
SHA-256 secure hash standard (DFIPS 180-2) implemented
using optimized [31mCONFIG_ARM[0m assembler and [31mCONFIG_NEON[0m, when available.
config [31mCONFIG_CRYPTO_SHA512_ARM[0m
tristate "SHA-384/512 digest algorithm (ARM-asm and NEON)"
select [31mCONFIG_CRYPTO_HASH[0m
depends on ![31mCONFIG_CPU_V7M[0m
help
SHA-512 secure hash standard (DFIPS 180-2) implemented
using optimized [31mCONFIG_ARM[0m assembler and [31mCONFIG_NEON[0m, when available.
config [31mCONFIG_CRYPTO_AES_ARM[0m
tristate "Scalar AES cipher for ARM"
select [31mCONFIG_CRYPTO_ALGAPI[0m
select [31mCONFIG_CRYPTO_AES[0m
help
Use optimized AES assembler routines for [31mCONFIG_ARM[0m platforms.
On [31mCONFIG_ARM[0m processors without the Crypto Extensions, this is the
fastest AES implementation for single blocks. For multiple
blocks, the [31mCONFIG_NEON[0m bit-sliced implementation is usually faster.
This implementation may be vulnerable to cache timing attacks,
since it uses lookup tables. However, as countermeasures it
disables IRQs and preloads the tables; it is hoped this makes
such attacks very difficult.
config [31mCONFIG_CRYPTO_AES_ARM_BS[0m
tristate "Bit sliced AES using NEON instructions"
depends on [31mCONFIG_KERNEL_MODE_NEON[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_LIB_AES[0m
select [31mCONFIG_CRYPTO_SIMD[0m
help
Use a faster and more secure [31mCONFIG_NEON[0m based implementation of AES in CBC,
CTR and XTS modes
Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
and for XTS mode encryption, CBC and XTS mode decryption speedup is
around 25%. (CBC encryption speed is not affected by this driver.)
This implementation does not rely on any lookup tables so it is
believed to be invulnerable to cache timing attacks.
config [31mCONFIG_CRYPTO_AES_ARM_CE[0m
tristate "Accelerated AES using ARMv8 Crypto Extensions"
depends on [31mCONFIG_KERNEL_MODE_NEON[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_LIB_AES[0m
select [31mCONFIG_CRYPTO_SIMD[0m
help
Use an implementation of AES in CBC, CTR and XTS modes that uses
ARMv8 Crypto Extensions
config [31mCONFIG_CRYPTO_GHASH_ARM_CE[0m
tristate "PMULL-accelerated GHASH using NEON/ARMv8 Crypto Extensions"
depends on [31mCONFIG_KERNEL_MODE_NEON[0m
select [31mCONFIG_CRYPTO_HASH[0m
select [31mCONFIG_CRYPTO_CRYPTD[0m
select [31mCONFIG_CRYPTO_GF128MUL[0m
help
Use an implementation of GHASH (used by the GCM AEAD chaining mode)
that uses the 64x64 to 128 bit polynomial multiplication (vmull.p64)
that is part of the ARMv8 Crypto Extensions, or a slower variant that
uses the vmull.p8 instruction that is part of the basic [31mCONFIG_NEON[0m [31mCONFIG_ISA[0m.
config [31mCONFIG_CRYPTO_CRCT10DIF_ARM_CE[0m
tristate "CRCT10DIF digest algorithm using PMULL instructions"
depends on [31mCONFIG_KERNEL_MODE_NEON[0m && [31mCONFIG_CRC_T10DIF[0m
select [31mCONFIG_CRYPTO_HASH[0m
config [31mCONFIG_CRYPTO_CRC32_ARM_CE[0m
tristate "CRC32(C) digest algorithm using CRC and/or PMULL instructions"
depends on [31mCONFIG_KERNEL_MODE_NEON[0m && [31mCONFIG_CRC32[0m
select [31mCONFIG_CRYPTO_HASH[0m
config [31mCONFIG_CRYPTO_CHACHA20_NEON[0m
tristate "NEON accelerated ChaCha stream cipher algorithms"
depends on [31mCONFIG_KERNEL_MODE_NEON[0m
select [31mCONFIG_CRYPTO_BLKCIPHER[0m
select [31mCONFIG_CRYPTO_CHACHA20[0m
config [31mCONFIG_CRYPTO_NHPOLY1305_NEON[0m
tristate "NEON accelerated NHPoly1305 hash function (for Adiantum)"
depends on [31mCONFIG_KERNEL_MODE_NEON[0m
select [31mCONFIG_CRYPTO_NHPOLY1305[0m
endif