# SPDX-License-Identifier: GPL-2.0
menu "Processor features"
choice
prompt "Endianness selection"
default [31mCONFIG_CPU_LITTLE_ENDIAN[0m
help
Some SuperH machines can be configured for either little or big
endian byte order. These modes require different kernels.
config [31mCONFIG_CPU_LITTLE_ENDIAN[0m
bool "Little Endian"
config [31mCONFIG_CPU_BIG_ENDIAN[0m
bool "Big Endian"
depends on ![31mCONFIG_CPU_SH5[0m
endchoice
config [31mCONFIG_SH_FPU[0m
def_bool y
prompt "FPU support"
depends on [31mCONFIG_CPU_HAS_FPU[0m
help
Selecting this option will enable support for SH processors that
have [31mCONFIG_FPU[0m units (ie, SH77xx).
This option must be set in order to enable the [31mCONFIG_FPU[0m.
config [31mCONFIG_SH64_FPU_DENORM_FLUSH[0m
bool "Flush floating point denorms to zero"
depends on [31mCONFIG_SH_FPU[0m && [31mCONFIG_SUPERH64[0m
config [31mCONFIG_SH_FPU_EMU[0m
def_bool n
prompt "FPU emulation support"
depends on ![31mCONFIG_SH_FPU[0m
help
Selecting this option will enable support for software [31mCONFIG_FPU[0m emulation.
Most SH-3 users will want to say Y here, whereas most SH-4 users will
want to say N.
config [31mCONFIG_SH_DSP[0m
def_bool y
prompt "DSP support"
depends on [31mCONFIG_CPU_HAS_DSP[0m
help
Selecting this option will enable support for SH processors that
have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP).
This option must be set in order to enable the DSP.
config [31mCONFIG_SH_ADC[0m
def_bool y
prompt "ADC support"
depends on [31mCONFIG_CPU_SH3[0m
help
Selecting this option will allow the Linux kernel to use SH3 on-chip
ADC module.
If unsure, say N.
config [31mCONFIG_SH_STORE_QUEUES[0m
bool "Support for Store Queues"
depends on [31mCONFIG_CPU_SH4[0m
help
Selecting this option will enable an in-kernel API for manipulating
the store queues integrated in the SH-4 processors.
config [31mCONFIG_SPECULATIVE_EXECUTION[0m
bool "Speculative subroutine return"
depends on [31mCONFIG_CPU_SUBTYPE_SH7780[0m || [31mCONFIG_CPU_SUBTYPE_SH7785[0m || [31mCONFIG_CPU_SUBTYPE_SH7786[0m
help
This enables support for a speculative instruction fetch for
subroutine return. There are various pitfalls associated with
this, as outlined in the SH7780 hardware manual.
If unsure, say N.
config [31mCONFIG_SH64_ID2815_WORKAROUND[0m
bool "Include workaround for SH5-101 cut2 silicon defect ID2815"
depends on [31mCONFIG_CPU_SUBTYPE_SH5_101[0m
config [31mCONFIG_CPU_HAS_INTEVT[0m
bool
config [31mCONFIG_CPU_HAS_IPR_IRQ[0m
bool
config [31mCONFIG_CPU_HAS_SR_RB[0m
bool
help
This will enable the use of SR.RB register bank usage. Processors
that are lacking this bit must have another method in place for
accomplishing what is taken care of by the banked registers.
See <file:Documentation/sh/register-banks.txt> for further
information on SR.RB and register banking in the kernel in general.
config [31mCONFIG_CPU_HAS_PTEAEX[0m
bool
config [31mCONFIG_CPU_HAS_DSP[0m
bool
config [31mCONFIG_CPU_HAS_FPU[0m
bool
endmenu