# SPDX-License-Identifier: GPL-2.0-only
#
# Performance Monitor Drivers
#
menu "Performance monitor support"
depends on [31mCONFIG_PERF_EVENTS[0m
config [31mCONFIG_ARM_CCI_PMU[0m
tristate "ARM CCI PMU driver"
depends on ([31mCONFIG_ARM[0m && [31mCONFIG_CPU_V7[0m) || [31mCONFIG_ARM64[0m
select [31mCONFIG_ARM_CCI[0m
help
Support for PMU events monitoring on the [31mCONFIG_ARM[0m CCI (Cache Coherent
Interconnect) family of products.
If compiled as a module, it will be called arm-cci.
config [31mCONFIG_ARM_CCI400_PMU[0m
bool "support CCI-400"
default y
depends on [31mCONFIG_ARM_CCI_PMU[0m
select [31mCONFIG_ARM_CCI400_COMMON[0m
help
CCI-400 provides 4 independent event counters counting events related
to the connected slave/master interfaces, plus a cycle counter.
config [31mCONFIG_ARM_CCI5xx_PMU[0m
bool "support CCI-500/CCI-550"
default y
depends on [31mCONFIG_ARM_CCI_PMU[0m
help
CCI-500/CCI-550 both provide 8 independent event counters, which can
count events pertaining to the slave/master interfaces as well as the
internal events to the CCI.
config [31mCONFIG_ARM_CCN[0m
tristate "ARM CCN driver support"
depends on [31mCONFIG_ARM[0m || [31mCONFIG_ARM64[0m
help
PMU (perf) driver supporting the [31mCONFIG_ARM[0m CCN (Cache Coherent Network)
interconnect.
config [31mCONFIG_ARM_PMU[0m
depends on [31mCONFIG_ARM[0m || [31mCONFIG_ARM64[0m
bool "ARM PMU framework"
default y
help
Say y if you want to use CPU performance monitors on [31mCONFIG_ARM[0m-based
systems.
config [31mCONFIG_ARM_PMU_ACPI[0m
depends on [31mCONFIG_ARM_PMU[0m && [31mCONFIG_ACPI[0m
def_bool y
config [31mCONFIG_ARM_SMMU_V3_PMU[0m
tristate "ARM SMMUv3 Performance Monitors Extension"
depends on [31mCONFIG_ARM64[0m && [31mCONFIG_ACPI[0m && [31mCONFIG_ARM_SMMU_V3[0m
help
Provides support for the [31mCONFIG_ARM[0m SMMUv3 Performance Monitor Counter
Groups (PMCG), which provide monitoring of transactions passing
through the SMMU and allow the resulting information to be filtered
based on the Stream ID of the corresponding master.
config [31mCONFIG_ARM_DSU_PMU[0m
tristate "ARM DynamIQ Shared Unit (DSU) PMU"
depends on [31mCONFIG_ARM64[0m
help
Provides support for performance monitor unit in [31mCONFIG_ARM[0m DynamIQ Shared
Unit (DSU). The DSU integrates one or more cores with an L3 memory
system, control logic. The PMU allows counting various events related
to DSU.
config [31mCONFIG_FSL_IMX8_DDR_PMU[0m
tristate "Freescale i.MX8 DDR perf monitor"
depends on [31mCONFIG_ARCH_MXC[0m
help
Provides support for the [31mCONFIG_DDR[0m performance monitor in i.MX8, which
can give information about memory throughput and other related
events.
config [31mCONFIG_HISI_PMU[0m
bool "HiSilicon SoC PMU"
depends on [31mCONFIG_ARM64[0m && [31mCONFIG_ACPI[0m
help
Support for HiSilicon SoC uncore performance monitoring
unit (PMU), such as: L3C, HHA and DDRC.
config [31mCONFIG_QCOM_L2_PMU[0m
bool "Qualcomm Technologies L2-cache PMU"
depends on [31mCONFIG_ARCH_QCOM[0m && [31mCONFIG_ARM64[0m && [31mCONFIG_ACPI[0m
help
Provides support for the L2 cache performance monitor unit (PMU)
in Qualcomm Technologies processors.
Adds the L2 cache PMU into the perf events subsystem for
monitoring L2 cache events.
config [31mCONFIG_QCOM_L3_PMU[0m
bool "Qualcomm Technologies L3-cache PMU"
depends on [31mCONFIG_ARCH_QCOM[0m && [31mCONFIG_ARM64[0m && [31mCONFIG_ACPI[0m
select [31mCONFIG_QCOM_IRQ_COMBINER[0m
help
Provides support for the L3 cache performance monitor unit (PMU)
in Qualcomm Technologies processors.
Adds the L3 cache PMU into the perf events subsystem for
monitoring L3 cache events.
config [31mCONFIG_THUNDERX2_PMU[0m
tristate "Cavium ThunderX2 SoC PMU UNCORE"
depends on [31mCONFIG_ARCH_THUNDER2[0m && [31mCONFIG_ARM64[0m && [31mCONFIG_ACPI[0m && [31mCONFIG_NUMA[0m
default m
help
Provides support for ThunderX2 UNCORE events.
The SoC has PMU support in its L3 cache controller (L3C) and
in the DDR4 Memory Controller (DMC).
config [31mCONFIG_XGENE_PMU[0m
depends on [31mCONFIG_ARCH_XGENE[0m
bool "APM X-Gene SoC PMU"
default n
help
Say y if you want to use [31mCONFIG_APM[0m X-Gene SoC performance monitors.
config [31mCONFIG_ARM_SPE_PMU[0m
tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
depends on [31mCONFIG_ARM64[0m
help
Enable perf support for the ARMv8.2 Statistical Profiling
Extension, which provides periodic sampling of operations in
the CPU pipeline and reports this via the perf AUX interface.
endmenu