# SPDX-License-Identifier: GPL-2.0-only config [31mCONFIG_PINCTRL_ASPEED[0m bool depends on ([31mCONFIG_ARCH_ASPEED[0m || [31mCONFIG_COMPILE_TEST[0m) && [31mCONFIG_OF[0m depends on [31mCONFIG_MFD_SYSCON[0m select [31mCONFIG_PINMUX[0m select [31mCONFIG_PINCONF[0m select [31mCONFIG_GENERIC_PINCONF[0m select [31mCONFIG_REGMAP_MMIO[0m config [31mCONFIG_PINCTRL_ASPEED_G4[0m bool "Aspeed G4 SoC pin control" depends on ([31mCONFIG_MACH_ASPEED_G4[0m || [31mCONFIG_COMPILE_TEST[0m) && [31mCONFIG_OF[0m select [31mCONFIG_PINCTRL_ASPEED[0m help Say Y here to enable pin controller support for Aspeed's 4th generation SoCs. GPIO is provided by a separate GPIO driver. config [31mCONFIG_PINCTRL_ASPEED_G5[0m bool "Aspeed G5 SoC pin control" depends on ([31mCONFIG_MACH_ASPEED_G5[0m || [31mCONFIG_COMPILE_TEST[0m) && [31mCONFIG_OF[0m select [31mCONFIG_PINCTRL_ASPEED[0m help Say Y here to enable pin controller support for Aspeed's 5th generation SoCs. GPIO is provided by a separate GPIO driver. config [31mCONFIG_PINCTRL_ASPEED_G6[0m bool "Aspeed G6 SoC pin control" depends on ([31mCONFIG_MACH_ASPEED_G6[0m || [31mCONFIG_COMPILE_TEST[0m) && [31mCONFIG_OF[0m select [31mCONFIG_PINCTRL_ASPEED[0m help Say Y here to enable pin controller support for Aspeed's 6th generation SoCs. GPIO is provided by a separate GPIO driver. |