* Freescale low power universal asynchronous receiver/transmitter (lpuart)

Required properties:
- compatible :
  - "fsl,vf610-lpuart" for lpuart compatible with the one integrated
    on Vybrid vf610 SoC with 8-bit register organization
  - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated
    on LS1021A SoC with 32-bit big-endian register organization
  - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated
    on i.MX7ULP SoC with 32-bit little-endian register organization
  - "fsl,imx8qxp-lpuart" for lpuart compatible with the one integrated
    on i.MX8QXP SoC with 32-bit little-endian register organization
- reg : Address and length of the register set for the device
- interrupts : Should contain uart interrupt
- clocks : phandle + clock specifier pairs, one for each entry in clock-names
- clock-names : For vf610/ls1021a/imx7ulp, "ipg" clock is for uart bus/baud
  clock. For imx8qxp lpuart, "ipg" clock is bus clock that is used to access
  lpuart controller registers, it also requires "baud" clock for module to
  receive/transmit data.

Optional properties:
- dmas: A list of two dma specifiers, one for each entry in dma-names.
- dma-names: should contain "tx" and "rx".
- rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
  linux,rs485-enabled-at-boot-time: see rs485.txt

Note: Optional properties for DMA support. Write them both or both not.

Example:

uart0: serial@40027000 {
		compatible = "fsl,vf610-lpuart";
		reg = <0x40027000 0x1000>;
		interrupts = <0 61 0x00>;
		clocks = <&clks VF610_CLK_UART0>;
		clock-names = "ipg";
		dmas = <&edma0 0 2>,
			<&edma0 0 3>;
		dma-names = "rx","tx";
	};