# SPDX-License-Identifier: GPL-2.0
menu "Memory management options"
config [31mCONFIG_MMU[0m
bool "Support for memory management hardware"
depends on ![31mCONFIG_CPU_SH2[0m
default y
help
Some SH processors (such as SH-2/SH-2A) lack an [31mCONFIG_MMU[0m. In order to
boot on these systems, this option must not be set.
On other systems (such as the SH-3 and 4) where an [31mCONFIG_MMU[0m exists,
turning this off will boot the kernel on these machines with the
[31mCONFIG_MMU[0m implicitly switched off.
config [31mCONFIG_PAGE_OFFSET[0m
hex
default "0x80000000" if [31mCONFIG_MMU[0m && [31mCONFIG_SUPERH32[0m
default "0x20000000" if [31mCONFIG_MMU[0m && [31mCONFIG_SUPERH64[0m
default "0x00000000"
config [31mCONFIG_FORCE_MAX_ZONEORDER[0m
int "Maximum zone order"
range 9 64 if [31mCONFIG_PAGE_SIZE_16KB[0m
default "9" if [31mCONFIG_PAGE_SIZE_16KB[0m
range 7 64 if [31mCONFIG_PAGE_SIZE_64KB[0m
default "7" if [31mCONFIG_PAGE_SIZE_64KB[0m
range 11 64
default "14" if ![31mCONFIG_MMU[0m
default "11"
help
The kernel memory allocator divides physically contiguous memory
blocks into "zones", where each zone is a power of two number of
pages. This option selects the largest power of two that the kernel
keeps in the memory allocator. If you need to allocate very large
blocks of physically contiguous memory, then you may need to
increase this value.
This config option is actually maximum order plus one. For example,
a value of 11 means that the largest free memory block is 2^10 pages.
The page size is not necessarily 4KB. Keep this in mind when
choosing a value for this option.
config [31mCONFIG_MEMORY_START[0m
hex "Physical memory start address"
default "0x08000000"
---help---
Computers built with Hitachi SuperH processors always
map the [31mCONFIG_ROM[0m starting at address zero. But the processor
does not specify the range that RAM takes.
The physical memory (RAM) start address will be automatically
set to 08000000. Other platforms, such as the Solution Engine
boards typically map RAM at 0C000000.
Tweak this only when porting to a new machine which does not
already have a defconfig. Changing it from the known correct
value on any of the known systems will only lead to disaster.
config [31mCONFIG_MEMORY_SIZE[0m
hex "Physical memory size"
default "0x04000000"
help
This sets the default memory size assumed by your SH kernel. It can
be overridden as normal by the 'mem=' argument on the kernel command
line. If unsure, consult your board specifications or just leave it
as 0x04000000 which was the default value before this became
configurable.
# Physical addressing modes
config [31mCONFIG_29BIT[0m
def_bool ![31mCONFIG_32BIT[0m
depends on [31mCONFIG_SUPERH32[0m
select [31mCONFIG_UNCACHED_MAPPING[0m
config [31mCONFIG_32BIT[0m
bool
default y if [31mCONFIG_CPU_SH5[0m || ![31mCONFIG_MMU[0m
config [31mCONFIG_PMB[0m
bool "Support 32-bit physical addressing through PMB"
depends on [31mCONFIG_MMU[0m && [31mCONFIG_CPU_SH4A[0m && ![31mCONFIG_CPU_SH4AL_DSP[0m
select [31mCONFIG_32BIT[0m
select [31mCONFIG_UNCACHED_MAPPING[0m
help
If you say Y here, physical addressing will be extended to
32-bits through the SH-4A [31mCONFIG_PMB[0m. If this is not set, legacy
29-bit physical addressing will be used.
config [31mCONFIG_X2TLB[0m
def_bool y
depends on ([31mCONFIG_CPU_SHX2[0m || [31mCONFIG_CPU_SHX3[0m) && [31mCONFIG_MMU[0m
config [31mCONFIG_VSYSCALL[0m
bool "Support vsyscall page"
depends on [31mCONFIG_MMU[0m && ([31mCONFIG_CPU_SH3[0m || [31mCONFIG_CPU_SH4[0m)
default y
help
This will enable support for the kernel mapping a vDSO page
in process space, and subsequently handing down the entry point
to the libc through the ELF auxiliary vector.
From the kernel side this is used for the signal trampoline.
For systems with an [31mCONFIG_MMU[0m that can afford to give up a page,
(the default value) say Y.
config [31mCONFIG_NUMA[0m
bool "Non Uniform Memory Access (NUMA) Support"
depends on [31mCONFIG_MMU[0m && [31mCONFIG_SYS_SUPPORTS_NUMA[0m
select [31mCONFIG_ARCH_WANT_NUMA_VARIABLE_LOCALITY[0m
default n
help
Some SH systems have many various memories scattered around
the address space, each with varying latencies. This enables
support for these blocks by binding them to nodes and allowing
memory policies to be used for prioritizing and controlling
allocation behaviour.
config [31mCONFIG_NODES_SHIFT[0m
int
default "3" if [31mCONFIG_CPU_SUBTYPE_SHX3[0m
default "1"
depends on [31mCONFIG_NEED_MULTIPLE_NODES[0m
config [31mCONFIG_ARCH_FLATMEM_ENABLE[0m
def_bool y
depends on ![31mCONFIG_NUMA[0m
config [31mCONFIG_ARCH_SPARSEMEM_ENABLE[0m
def_bool y
select [31mCONFIG_SPARSEMEM_STATIC[0m
config [31mCONFIG_ARCH_SPARSEMEM_DEFAULT[0m
def_bool y
config [31mCONFIG_ARCH_SELECT_MEMORY_MODEL[0m
def_bool y
config [31mCONFIG_ARCH_ENABLE_MEMORY_HOTPLUG[0m
def_bool y
depends on [31mCONFIG_SPARSEMEM[0m && [31mCONFIG_MMU[0m
config [31mCONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE[0m
def_bool y
depends on [31mCONFIG_SPARSEMEM[0m && [31mCONFIG_MMU[0m
config [31mCONFIG_ARCH_MEMORY_PROBE[0m
def_bool y
depends on [31mCONFIG_MEMORY_HOTPLUG[0m
config [31mCONFIG_IOREMAP_FIXED[0m
def_bool y
depends on [31mCONFIG_X2TLB[0m || [31mCONFIG_SUPERH64[0m
config [31mCONFIG_UNCACHED_MAPPING[0m
bool
config [31mCONFIG_HAVE_SRAM_POOL[0m
bool
select [31mCONFIG_GENERIC_ALLOCATOR[0m
choice
prompt "Kernel page size"
default [31mCONFIG_PAGE_SIZE_4KB[0m
config [31mCONFIG_PAGE_SIZE_4KB[0m
bool "4kB"
help
This is the default page size used by all SuperH CPUs.
config [31mCONFIG_PAGE_SIZE_8KB[0m
bool "8kB"
depends on ![31mCONFIG_MMU[0m || [31mCONFIG_X2TLB[0m
help
This enables 8kB pages as supported by SH-X2 and later MMUs.
config [31mCONFIG_PAGE_SIZE_16KB[0m
bool "16kB"
depends on ![31mCONFIG_MMU[0m
help
This enables 16kB pages on [31mCONFIG_MMU[0m-less SH systems.
config [31mCONFIG_PAGE_SIZE_64KB[0m
bool "64kB"
depends on ![31mCONFIG_MMU[0m || [31mCONFIG_CPU_SH4[0m || [31mCONFIG_CPU_SH5[0m
help
This enables support for 64kB pages, possible on all SH-4
CPUs and later.
endchoice
choice
prompt "HugeTLB page size"
depends on [31mCONFIG_HUGETLB_PAGE[0m
default [31mCONFIG_HUGETLB_PAGE_SIZE_1MB[0m if [31mCONFIG_PAGE_SIZE_64KB[0m
default [31mCONFIG_HUGETLB_PAGE_SIZE_64K[0m
config [31mCONFIG_HUGETLB_PAGE_SIZE_64K[0m
bool "64kB"
depends on ![31mCONFIG_PAGE_SIZE_64KB[0m
config [31mCONFIG_HUGETLB_PAGE_SIZE_256K[0m
bool "256kB"
depends on [31mCONFIG_X2TLB[0m
config [31mCONFIG_HUGETLB_PAGE_SIZE_1MB[0m
bool "1MB"
config [31mCONFIG_HUGETLB_PAGE_SIZE_4MB[0m
bool "4MB"
depends on [31mCONFIG_X2TLB[0m
config [31mCONFIG_HUGETLB_PAGE_SIZE_64MB[0m
bool "64MB"
depends on [31mCONFIG_X2TLB[0m
config [31mCONFIG_HUGETLB_PAGE_SIZE_512MB[0m
bool "512MB"
depends on [31mCONFIG_CPU_SH5[0m
endchoice
config [31mCONFIG_SCHED_MC[0m
bool "Multi-core scheduler support"
depends on [31mCONFIG_SMP[0m
default y
help
Multi-core scheduler support improves the CPU scheduler's decision
making when dealing with multi-core CPU chips at a cost of slightly
increased overhead in some places. If unsure say N here.
endmenu
menu "Cache configuration"
config [31mCONFIG_SH7705_CACHE_32KB[0m
bool "Enable 32KB cache size for SH7705"
depends on [31mCONFIG_CPU_SUBTYPE_SH7705[0m
default y
choice
prompt "Cache mode"
default [31mCONFIG_CACHE_WRITEBACK[0m if [31mCONFIG_CPU_SH2A[0m || [31mCONFIG_CPU_SH3[0m || [31mCONFIG_CPU_SH4[0m || [31mCONFIG_CPU_SH5[0m
default [31mCONFIG_CACHE_WRITETHROUGH[0m if ([31mCONFIG_CPU_SH2[0m && ![31mCONFIG_CPU_SH2A[0m)
config [31mCONFIG_CACHE_WRITEBACK[0m
bool "Write-back"
config [31mCONFIG_CACHE_WRITETHROUGH[0m
bool "Write-through"
help
Selecting this option will configure the caches in write-through
mode, as opposed to the default write-back configuration.
Since there's sill some aliasing issues on SH-4, this option will
unfortunately still require the majority of flushing functions to
be implemented to deal with aliasing.
If unsure, say N.
config [31mCONFIG_CACHE_OFF[0m
bool "Off"
endchoice
endmenu