# SPDX-License-Identifier: GPL-2.0-only
config [31mCONFIG_ARCH_HAS_RESET_CONTROLLER[0m
bool
menuconfig [31mCONFIG_RESET_CONTROLLER[0m
bool "Reset Controller Support"
default y if [31mCONFIG_ARCH_HAS_RESET_CONTROLLER[0m
help
Generic Reset Controller support.
This framework is designed to abstract reset handling of devices
via GPIOs or SoC-internal reset controller modules.
If unsure, say no.
if [31mCONFIG_RESET_CONTROLLER[0m
config [31mCONFIG_RESET_A10SR[0m
tristate "Altera Arria10 System Resource Reset"
depends on [31mCONFIG_MFD_ALTERA_A10SR[0m
help
This option enables support for the external reset functions for
peripheral PHYs on the Altera Arria10 System Resource Chip.
config [31mCONFIG_RESET_ATH79[0m
bool "AR71xx Reset Driver" if [31mCONFIG_COMPILE_TEST[0m
default [31mCONFIG_ATH79[0m
help
This enables the [31mCONFIG_ATH79[0m reset controller driver that supports the
AR71xx SoC reset controller.
config [31mCONFIG_RESET_AXS10X[0m
bool "AXS10x Reset Driver" if [31mCONFIG_COMPILE_TEST[0m
default [31mCONFIG_ARC_PLAT_AXS10X[0m
help
This enables the reset controller driver for AXS10x.
config [31mCONFIG_RESET_BERLIN[0m
bool "Berlin Reset Driver" if [31mCONFIG_COMPILE_TEST[0m
default [31mCONFIG_ARCH_BERLIN[0m
help
This enables the reset controller driver for Marvell Berlin SoCs.
config [31mCONFIG_RESET_BRCMSTB[0m
tristate "Broadcom STB reset controller"
depends on [31mCONFIG_ARCH_BRCMSTB[0m || [31mCONFIG_COMPILE_TEST[0m
default [31mCONFIG_ARCH_BRCMSTB[0m
help
This enables the reset controller driver for Broadcom STB SoCs using
a SUN_TOP_CTRL_SW_INIT style controller.
config [31mCONFIG_RESET_HSDK[0m
bool "Synopsys HSDK Reset Driver"
depends on [31mCONFIG_HAS_IOMEM[0m
depends on [31mCONFIG_ARC_SOC_HSDK[0m || [31mCONFIG_COMPILE_TEST[0m
help
This enables the reset controller driver for HSDK board.
config [31mCONFIG_RESET_IMX7[0m
bool "i.MX7/8 Reset Driver" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_HAS_IOMEM[0m
default [31mCONFIG_SOC_IMX7D[0m || ([31mCONFIG_ARM64[0m && [31mCONFIG_ARCH_MXC[0m)
select [31mCONFIG_MFD_SYSCON[0m
help
This enables the reset controller driver for i.MX7 SoCs.
config [31mCONFIG_RESET_LANTIQ[0m
bool "Lantiq XWAY Reset Driver" if [31mCONFIG_COMPILE_TEST[0m
default [31mCONFIG_SOC_TYPE_XWAY[0m
help
This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
config [31mCONFIG_RESET_LPC18XX[0m
bool "LPC18xx/43xx Reset Driver" if [31mCONFIG_COMPILE_TEST[0m
default [31mCONFIG_ARCH_LPC18XX[0m
help
This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
config [31mCONFIG_RESET_MESON[0m
bool "Meson Reset Driver" if [31mCONFIG_COMPILE_TEST[0m
default [31mCONFIG_ARCH_MESON[0m
help
This enables the reset driver for Amlogic Meson SoCs.
config [31mCONFIG_RESET_MESON_AUDIO_ARB[0m
tristate "Meson Audio Memory Arbiter Reset Driver"
depends on [31mCONFIG_ARCH_MESON[0m || [31mCONFIG_COMPILE_TEST[0m
help
This enables the reset driver for Audio Memory Arbiter of
Amlogic's A113 based SoCs
config [31mCONFIG_RESET_OXNAS[0m
bool
config [31mCONFIG_RESET_PISTACHIO[0m
bool "Pistachio Reset Driver" if [31mCONFIG_COMPILE_TEST[0m
default [31mCONFIG_MACH_PISTACHIO[0m
help
This enables the reset driver for ImgTec Pistachio SoCs.
config [31mCONFIG_RESET_QCOM_AOSS[0m
bool "Qcom AOSS Reset Driver"
depends on [31mCONFIG_ARCH_QCOM[0m || [31mCONFIG_COMPILE_TEST[0m
help
This enables the AOSS (always on subsystem) reset driver
for Qualcomm SDM845 SoCs. Say Y if you want to control
reset signals provided by AOSS for Modem, Venus, ADSP,
GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
config [31mCONFIG_RESET_QCOM_PDC[0m
tristate "Qualcomm PDC Reset Driver"
depends on [31mCONFIG_ARCH_QCOM[0m || [31mCONFIG_COMPILE_TEST[0m
help
This enables the PDC (Power Domain Controller) reset driver
for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
to control reset signals provided by PDC for Modem, Compute,
Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
config [31mCONFIG_RESET_SCMI[0m
tristate "Reset driver controlled via ARM SCMI interface"
depends on [31mCONFIG_ARM_SCMI_PROTOCOL[0m || [31mCONFIG_COMPILE_TEST[0m
default [31mCONFIG_ARM_SCMI_PROTOCOL[0m
help
This driver provides support for reset signal/domains that are
controlled by firmware that implements the SCMI interface.
This driver uses SCMI Message Protocol to interact with the
firmware controlling all the reset signals.
config [31mCONFIG_RESET_SIMPLE[0m
bool "Simple Reset Controller Driver" if [31mCONFIG_COMPILE_TEST[0m
default [31mCONFIG_ARCH_STM32[0m || [31mCONFIG_ARCH_STRATIX10[0m || [31mCONFIG_ARCH_SUNXI[0m || [31mCONFIG_ARCH_ZX[0m || [31mCONFIG_ARCH_ASPEED[0m || [31mCONFIG_ARCH_BITMAIN[0m || [31mCONFIG_ARC[0m
help
This enables a simple reset controller driver for reset lines that
that can be asserted and deasserted by toggling bits in a contiguous,
exclusive register space.
Currently this driver supports:
- Altera SoCFPGAs
- ASPEED BMC SoCs
- RCC reset controller in STM32 MCUs
- Allwinner SoCs
- ZTE's zx2967 family
- Bitmain BM1880 SoC
config [31mCONFIG_RESET_STM32MP157[0m
bool "STM32MP157 Reset Driver" if [31mCONFIG_COMPILE_TEST[0m
default [31mCONFIG_MACH_STM32MP157[0m
help
This enables the RCC reset controller driver for STM32 MPUs.
config [31mCONFIG_RESET_SOCFPGA[0m
bool "SoCFPGA Reset Driver" if [31mCONFIG_COMPILE_TEST[0m && ![31mCONFIG_ARCH_SOCFPGA[0m
default [31mCONFIG_ARCH_SOCFPGA[0m
select [31mCONFIG_RESET_SIMPLE[0m
help
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
driver gets initialized early during platform init calls.
config [31mCONFIG_RESET_SUNXI[0m
bool "Allwinner SoCs Reset Driver" if [31mCONFIG_COMPILE_TEST[0m && ![31mCONFIG_ARCH_SUNXI[0m
default [31mCONFIG_ARCH_SUNXI[0m
select [31mCONFIG_RESET_SIMPLE[0m
help
This enables the reset driver for Allwinner SoCs.
config [31mCONFIG_RESET_TI_SCI[0m
tristate "TI System Control Interface (TI-SCI) reset driver"
depends on [31mCONFIG_TI_SCI_PROTOCOL[0m
help
This enables the reset driver support over TI System Control Interface
available on some new TI's SoCs. If you wish to use reset resources
managed by the TI System Controller, say Y here. Otherwise, say N.
config [31mCONFIG_RESET_TI_SYSCON[0m
tristate "TI SYSCON Reset Driver"
depends on [31mCONFIG_HAS_IOMEM[0m
select [31mCONFIG_MFD_SYSCON[0m
help
This enables the reset driver support for TI devices with
memory-mapped reset registers as part of a syscon device node. If
you wish to use the reset framework for such memory-mapped devices,
say Y here. Otherwise, say N.
config [31mCONFIG_RESET_UNIPHIER[0m
tristate "Reset controller driver for UniPhier SoCs"
depends on [31mCONFIG_ARCH_UNIPHIER[0m || [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_OF[0m && [31mCONFIG_MFD_SYSCON[0m
default [31mCONFIG_ARCH_UNIPHIER[0m
help
Support for reset controllers on UniPhier SoCs.
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
config [31mCONFIG_RESET_UNIPHIER_GLUE[0m
tristate "Reset driver in glue layer for UniPhier SoCs"
depends on ([31mCONFIG_ARCH_UNIPHIER[0m || [31mCONFIG_COMPILE_TEST[0m) && [31mCONFIG_OF[0m
default [31mCONFIG_ARCH_UNIPHIER[0m
select [31mCONFIG_RESET_SIMPLE[0m
help
Support for peripheral core reset included in its own glue layer
on UniPhier SoCs. Say Y if you want to control reset signals
provided by the glue layer.
config [31mCONFIG_RESET_ZYNQ[0m
bool "ZYNQ Reset Driver" if [31mCONFIG_COMPILE_TEST[0m
default [31mCONFIG_ARCH_ZYNQ[0m
help
This enables the reset controller driver for Xilinx Zynq SoCs.
source "drivers/reset/sti/Kconfig"
source "drivers/reset/hisilicon/Kconfig"
source "drivers/reset/tegra/Kconfig"
endif