Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 76 files:
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp, line 102
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp, line 27
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUMIRFormatter.cpp, line 24
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h, line 18
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/GCNRegPressure.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/GCNSubtarget.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
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- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIFrameLowering.h, line 19
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIISelLowering.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIInstrInfo.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIPostRABundler.cpp, line 125
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp, line 1891
- external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h